P4C1299/P4C1299L
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Output Enable (OE) & Chip Enable (CE
1
and
CE
2
)
Control Functions
Data Retention with 2.0V Supply (P4C1299L)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
DESCRIPTIOn
The P4C1299 and P4C1299L are a 262,144-bit ultra high-
speed static RAM organized as 64K x 4. The CMOS memory
requires no clock or refreshing and has equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAM operates from a single 5V±10% tolerance power
supply. With battery backup (P4C1299L Only), data integrity
is maintained for supply voltages down to 2.0V. Current
drain is typically 10 µA from a 2.0V supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1299 and P4C1299L are available in a 28-pin
300 mil DIP or SOJ, as well as a 28-pin 350x550 mil LCC
package, providing excellent board level densities.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, C5)
SOJ (J5)
LCC (L5)
Document #
SRAM144
REV OR
Created Nov 2012
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
5
7
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C1299
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
MIL
IND/COM
MIL
P4C1299L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
Unit
V
V
V
V
V
V
V
Input Clamp Diode Voltage V
CC
= Min, I
IN
= 18 mA
Output Low Voltage (TTL
Load)
Output High Voltage (TTL
Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min
I
OH
= -4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
-10
-5
-10
-5
—
—
—
—
+10
+5
+10
+5
40
30
15
10
-10
-5
-10
-5
—
—
—
—
+10
µA
+5
+10
µA
+5
35
mA
30
10
mA
8
I
LI
I
LO
Output Leakage Current
V
CC
= Max, V
OUT
= GND to V
CC
IND/COM
MIL
IND/COM
MIL
IND/COM
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
1,2
≥ V
IN
, V
CC
= Max, f =
Max, Outputs Open
CE
1,2
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
Standby Power Supply
Current (CMOS Input
Levels)
N/A = Not applicable
Document #
SRAM144
REV OR
Page 2
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic Operating Current*
Temperature Range
Commercial
Industrial
Military
-15
160
160
160
-20
125
135
150
-25
115
120
120
-35
110
115
120
-45
110
115
120
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1,2
= V
IL
DATA RETEnTIOn CHARACTERISTICS (P4C1299L Only)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
1,2
≥ V
CC
-0.2V,
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
1000
2000
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEnTIOn WAVEFORM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down
0
15
0
9
0
20
3
3
8
8
0
9
0
25
-15
Min
15
15
15
3
3
10
10
0
15
0
35
Max
Min
20
20
20
3
3
15
15
0
20
0
45
-20
Max
Min
25
25
25
3
3
15
25
0
20
-25
Max
Min
35
35
35
3
3
20
30
-35
Max
Min
45
45
45
-45
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 3
Document #SRAM144 REV OR
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(5)
TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
(5,6)
TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE
1,2
COnTROLLED)
(5,6)
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
CE
1
and CE
2
are LOW and
WE
is HIGH for READ cycle.
6.
WE is
HIGH and ADDRESS must be valid prior to, or coincident with
CE
1
and CE
2
transitions
LOW.
7. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM144
REV OR
Page 4
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
0
-15
Min
10
8
8
0
8
0
7
0
6
0
Max
12
10
10
0
10
0
8
0
7
0
-20
Min
Max
15
12
12
0
12
0
10
0
8
0
-25
Min
Max
20
15
15
0
15
0
12
0
10
0
-35
Min
Max
25
18
18
0
18
0
15
0
15
-45
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(9)
Notes:
10.
CE
1,2
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
1,2
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #SRAM144 REV OR
Page 5
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