PYA28HC256
HIGH SPEED 32K x 8 EEPROM
FEATURES
Access Times of 70, 90 and 120ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 80 mA Active Current
- 3 mA Standby Current
Fast Write Cycle Times
Software Data Protection
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTIOn
The PYA28HC256 is a 5 Volt 32Kx8 EEPROM. The device
supports 64-byte page write operation. The PYA28HC256
features
DATA
and Toggle Bit Polling as well as a system
software scheme used to indicate early completion of a
Write Cycle. The device also includes user-optional soft-
ware data protection. Data Retention is 10 Years. The
device is available in a 28-Pin 600 mil wide Ceramic DIP
and 32-Pin LCC.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOn
DIP (C5-1)
LCC (L6)
Document #
EEPROM106
REV 03
Revised October 2014
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
OPERATIOn
READ
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
BYTE WRITE
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The PYA28HC256 supports both
a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
which-
ever occurs last. Similarly, the data is latched internally
by the rising edge of either
CE
or
WE,
whichever occurs
first. A byte write operation, once initiated, will automati-
cally continue to completion.
PAgE WRITE
The page write feature of the PYA28HC256 allows 1
to 64 bytes of data to be consecutively written to the
PYA28HC256 during a single internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A
6
through A
14
) for each
subsequent valid write cycle to the part during this opera-
tion must be the same as the initial page address. The
bytes within the page to be written are specified with the
A
0
through A
5
inputs.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional 1 to 63 bytes in the same man-
ner as the first byte was written. Each successive byte
load cycle, started by the
WE
HIGH to LOW transition,
must begin within 150µs of the falling edge of the pre-
ceding
WE.
If a subsequent
WE
HIGH to LOW transition
is not detected within 150µs, the internal automatic pro-
gramming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 150µs.
WRITE STATUS BITS
The PYA28HC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus
as shown below.
DATA POLLIng
The PYA28HC256 features
DATA
Polling as a meth-
od to indicate to the host system that the byte write or
page write cycle has completed.
DATA
Polling allows a
simple bit test operation to determine the status of the
PYA28HC256, eliminating additional interrupts or external
hardware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the comple-
ment of that data on I/O
7
(i.e., write data=0xxx xxxx, read
data=1xxx xxxx). Once the programming cycle is com-
plete, I/O
7
will reflect true data. Note: If the PYA28HC256
is in the protected state and an illegal write operation is
attempted,
DATA
Polling will not operate.
TOggLE BIT
The PYA28HC256 also provides another method for de-
termining when the internal write cycle is complete. Dur-
ing the internal programming cycle, I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent attempts
to read the device. When the internal cycle is complete
the toggling will cease and the device will be accessible
for addtional read or write operations.
DATA PROTECTIOn
Pyramid has incorporated both hardware and software
features that will protect the memory against inadvertent
writes during transitions of the host system power sup-
ply.
Hardware Protection
Hardware features protect against inadvertent writes to
the PYA28C256 in the following ways: (a) VCC sense - if
VCC is below 3.8V (typical) the write function is inhibited;
(b) VCC power-on delay - once VCC has reached 3.8V
the device will automatically time out 5 ms (typical) before
allowing a write; (c) write inhibit - holding any one of OE
low, CE high or WE high inhibits write cycles; and (d)
noise filter - pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a write cycle.
Software Data Protection
A software controlled data protection feature has been
implemented on the PYA28C256. When enabled, the
software data protection (SDP), will prevent inadvertent
writes. The SDP feature may be enabled or disabled by
the user; the PYA28C256 is shipped from Pyramid with
SDP disabled.
SDP is enabled by the host system issuing a series of
Document #
EEPROM106
REV 03
Page 2
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
three write commands; three specific bytes of data are
written to the three specific addresses (refer to "Software
Data Protection" algorithm). After writing the 3-byte com-
mand sequence and after tWC the entire PYA28C256
will be protected against inadvertent write operations. It
should be noted, that once protected the host may still
perform a byte or page write to the PYA28C256. This
is done by preceding the data to be written by the same
3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the PYA28C256 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifi-
cations. The data in the enable and disable command
sequences is not written to the device and the memory
addresses used in the sequence may be written with data
in either a byte or page write operation.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; howev-
er, for the duration of tWC, read operations will effectively
be polling operations.
DEVICE IDEnTIFICATIOn
An extra 64 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12V
± 0.5V and using address locations 7FC0H to 7FFFH
the additional bytes may be written to or read from in the
same manner as the regular memory array.
OPTIOnAL CHIP ERASE MODE
The entire device can be erased using a 6-byte software
code. Please see "Software Chip Erase" application note
at the end of this datasheet for details.
Document #
EEPROM106
REV 03
Page 3
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
6.25V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.3 to +6.25
-0.5 to +6.25
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Military
Ambient Temp
-55°C to +125°C
gnD
0V
V
CC
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
I
LI
I
LO
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current
Output Leakage Current
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
Min
2.0
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
I
OL
= +2.1 mA, V
CC
= Min
I
OH
= -0.4 mA, V
CC
= Min
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥ V
IH
,
OE
= V
IL
,
I
SB
Standby Power Supply Current (TTL Input Levels)
V
CC
= Max,
f = Max, Outputs Open
CE
≥ V
HC
,
I
SB1
Standby Power Supply Current (CMOS Input Levels)
V
CC
= Max,
f = 0, Outputs Open,
V
IN
≤ V
LC
or V
IN
≥ V
HC
CE
=
OE
= V
IL
,
I
CC
Supply Current
WE
= V
IH
,
All I/O's = Open,
Inputs = V
CC
= 5.5V
notes:
—
—
90, 120ns
70ns
Max
V
CC
+ 0.3
0.8
V
CC
+ 0.5
0.2
0.45
Unit
V
V
V
V
V
V
2.4
-10
-10
—
+10
+10
3
60
µA
µA
mA
mA
300
µA
80
mA
1. Stresses greater than those listed under
MAxIMuM RAtINGS
may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than -3.0V and -100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
Document #
EEPROM106
REV 03
Page 4
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
POWER-UP TIMIng
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read operation
Power-up to Write operation
Max
100
5
Unit
µs
ms
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
AVAV
t
AVQV
t
ELQV
t
OLQV
t
ELQx
t
EHQZ
t
OLQx
t
OHQZ
t
AVQx
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address Change
0
0
35
0
0
35
0
40
0
-70
Min
70
70
70
35
0
40
0
50
Max
Min
90
90
90
40
0
50
-90
Max
Min
120
120
120
50
-120
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF READ CYCLE
Document #
EEPROM106
REV 03
Page 5
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