EEWORLDEEWORLDEEWORLD

Part Number

Search

SFS0863C-LF

Description
Fixed Frequency Synthesizer Surface Mount Module
File Size65KB,2 Pages
ManufacturerZ-Communications, Inc.
Websitehttps://www.zcomm.com/
Download Datasheet View All

SFS0863C-LF Overview

Fixed Frequency Synthesizer Surface Mount Module

SFS0863C-LF
Rev A1
Fixed Frequency Synthesizer
Surface Mount Module
Applications
• Basestations
• Test Instrumentation
Application Notes
• AN-107: Manual Soldering Technique
• AN-205: Measuring Phase Noise for SFS Series
Performance Specifications
Frequency
Phase Noise @ 10 kHz offset (1 Hz BW)
Harmonic Suppression (2nd)
Spurious Suppression
Power Output
Load Impedance
Settling Time
Operating Temperature Range
Package Style
Min
863.5
Typ
-118
-15
-70
Max
863.5
Units
MHz
dBc/Hz
dBc
dBc
-2
0
50
3
2
dBm
mS
-40
PLL-V12C
85
°C
Power Supply Requirements
Supply Voltage 1: PLL (Vcc, nom)
Supply Voltage 2: VCO (Vcc, nom)
Supply Current 1: PLL (Icc, typ)
Supply Current 2: VCO (Icc, typ)
Min
3.0
4.80
Typ
3
5
14
25
Max
3.5
5.15
Units
Vdc
Vdc
mA
mA
Reference Oscillator Signal
Frequency
Phase Noise @1 kHz Offset
Min
Typ
40
-145
Max
Units
MHz
dBc/Hz
Additional Notes
LFSuffix = RoHS Compliant. All specifications are subject to change without notice.
© Z-Communications, Inc. All Rights Reserved.
14118 Stowe Drive, Suite B | Poway, CA 92064 | TEL: (858) 621-2700 | FAX: (858) 486-1927
URL: www.zcomm.com | EMAIL: applications@zcomm.com
Page 1 of 2
FRM-S-002 B
About the use of S3C44B0X data port
#define TP_DCLK(a) outw((inw(S3C44B0X_PDATF) &(~(1<<8)) ) | ((a&1)<<8),S3C44B0X_PDATF) In this macro statement, do I need to set GPGF as an input port before using inw(S3C44B0X_PDATF)? Then I can ((in...
rushi1980 Embedded System
Recruiting part-time personnel for driver development
Our company is now recruiting authors of books on driver development. The salary is generous. If you are interested, you can contact me for details. QQ878298915. Please indicate the driver. Email pyq_...
chang0044 Embedded System
EE, you have made progress again
EE, you have made progress again. It has been a while since we last saw you. The mobile version of the forum is getting more and more powerful and easy to use. Keep it up. We can all see your progress...
Sur Talking
modelsim6.2 waveform
I use Modelsim se plus 6.2b to simulate Verilog program. The compilation is normal, but every time when I display the waveform, it is very strange. There is a waveform, but each signal always has only...
sxtz531 FPGA/CPLD
I am new to platformbuilder. After configuring, builder error occurs. I hope experts can give me some advice. Thank you.
--------------------Configuration: WINDOWSCE - EMULATOR: X86 Win32 (WCE emulator) Release-------------------- Generating platform header files... CEBUILD: Deleting old build logs CEBUILD: Skipping dir...
feitian9215 Embedded System
New dual-loop 900MHz and 1800MHz frequency band digital tuning system
A new dual-loop digital tuning system for 900MHz and 1800MHz frequency bands Abstract: A new digital tuning system consisting of DDS + dual PLL is studied : A loop generates the clock signal required ...
feifei Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 881  1925  331  191  662  18  39  7  4  14 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号