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STUD20N15

Description
Super high dense cell design for low RDS(ON).
File Size104KB,8 Pages
ManufacturerSAMHOP
Websitehttp://www.samhop.com.tw
Download Datasheet View All

STUD20N15 Overview

Super high dense cell design for low RDS(ON).

Gre
r
Pro
STU/D20N15
Ver 1.0
S a mHop Microelectronics C orp.
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
150V
I
D
20A
R
DS(ON)
(m
Ω
) Typ
58
@
VGS=10V
65
@
VGS=4.5V
FEATURES
Super high dense cell design for low R
DS(ON)
.
Rugged and reliable.
TO-252 and TO-251 Package.
G
S
G
D
S
STU SERIES
TO - 252AA( D - PAK )
STD SERIES
TO - 251 ( I - PAK )
ABSOLUTE MAXIMUM RATINGS (
T
C
=25
°
C unless otherwise noted
)
Symbol
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
a
c
Limit
150
±20
T
C
=25°C
T
C
=70°C
20
16.8
59
0.211
T
C
=25°C
T
C
=70°C
50
35
-55 to 175
Units
V
V
A
A
A
mJ
W
W
°C
Single Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JC
R
JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
3
50
°C/W
°C/W
Details are subject to change without notice.
Mar,16,2012
1
www.samhop.com.tw
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