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8SLVP1204ANLGI

Description
Low Skew Clock Driver, 8S Series, 4 True Output(s), 0 Inverted Output(s)
Categorylogic    logic   
File Size1MB，25 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
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8SLVP1204ANLGI Overview

Low Skew Clock Driver, 8S Series, 4 True Output(s), 0 Inverted Output(s)

8SLVP1204ANLGI Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerRenesas Electronics Corporation
package instructionHQCCN, LCC16,.12SQ,20
Reach Compliance Codecompliant
series8S
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-XQCC-N16
JESD-609 codee3
length3 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHQCCN
Encapsulate equivalent codeLCC16,.12SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup0.32 ns
propagation delay (tpd)0.32 ns
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.025 ns
Maximum seat height1.05 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width3 mm

8SLVP1204ANLGI Preview

Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for clock distribution applications that
demand well-defined performance and repeatability. Two selectable
differential inputs and four low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
8SLVP1204
DATASHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See
Applications Information, “Wiring the Differential Input
to Accept Single-Ended Levels”
(Figures 1A and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (I
EE
): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFPN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature
105°C operations
Block Diagram
V
CC
Pin Assignment
nQ3
nQ2
Q3
Q2
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
EE
1
SEL
2
16 15 14 13
12 nQ1
11 Q1
10 nQ0
9 Q0
5
V
CC
PCLK1 3
nPCLK1 4
6
PCLK0
0
1
f
REF
7
nPCLK0
8
V
REF
V
CC
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
8SLVP1204
16-Lead, 3mm x 3mm VFQFPN Package
SEL
V
REF
Pulldown
Voltage
Reference
IDT8SLVP1204 NOVEMBER 29, 2018
1
©2018 Integrated Device Technology, Inc.
8SLVP1204 DATASHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
V
EE
SEL
PCLK1
nPCLK1
V
CC
PCLK0
nPCLK0
V
REF
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Power
Input
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pin.
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface
levels.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
Power supply pins.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
Bias voltage reference for the PCLK inputs.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL
0 (default)
1
Operation
PCLK0, nPCLK0 is the selected differential clock input.
PCLK1, nPCLK1 is the selected differential clock input.
NOTE: SEL is an asynchronous control.
IDT8SLVP1204 NOVEMBER 29, 2018
2
©2018 Integrated Deice Technology, Inc.
8SLVP1204 DATASHEET
Absolute Maximum Ratings
Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of
the product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics
is not implied.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
150°C
-65°C to 150°C
2000V
1500V
Recommended Operating Conditions
Symbol
T
A
T
J
Parameter
Ambient air temperature
Junction temperature
Minimum
-40
Typical
Maximum
85
125
Units
C
C
NOTE 1: It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.
NOTE 2: All conditions in the table must be met to guarantee device functionality.
NOTE 3: The device is verified to the maximum operating junction temperature through simulation.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
2.97
Typical
3.3V
53
170
Maximum
3.63
60
204
Units
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
53
170
Maximum
3.465
60
204
Units
V
mA
mA
IDT8SLVP1204 NOVEMBER 29, 2018
3
©2018 Integrated Device Technology, Inc.
8SLVP1204 DATASHEET
Table 4C. Power Supply DC Characteristics,
V
CC
= 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
49
170
Maximum
2.625
55
199
Units
V
mA
mA
Table 4D. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.63V
V
CC
= 2.625V
V
CC
= 3.63V
V
CC
= 2.625V
SEL
SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
Input Low Voltage
Input High Current
Input Low Current
Table 4E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ±5% or 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= 3.465V
V
CC
= 2.625V
SEL
SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
Input Low Voltage
Input High Current
Input Low Current
IDT8SLVP1204 NOVEMBER 29, 2018
4
©2018 Integrated Device Technology, Inc.
8SLVP1204 DATASHEET
Table 4F. LVPECL DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
Input Low Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 3.63V
V
CC
= 3.63V, V
IN
= 0V
V
CC
= 3.63V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.65
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
Table 4G. LVPECL DC Characteristics,
V
CC
= 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
Input Low Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.65
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
Table 4H. LVPECL DC Characteristics,
V
CC
= 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
Input Low Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
IDT8SLVP1204 NOVEMBER 29, 2018
5
©2018 Integrated Device Technology, Inc.
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8SLVP1204ANLGI Related Products

8SLVP1204ANLGI 8SLVP1204ANLGI8
Description Low Skew Clock Driver, 8S Series, 4 True Output(s), 0 Inverted Output(s) Low Skew Clock Driver, 8S Series, 4 True Output(s), 0 Inverted Output(s)
Is it Rohs certified? conform to conform to
Maker Renesas Electronics Corporation Renesas Electronics Corporation
package instruction HQCCN, LCC16,.12SQ,20 HQCCN, LCC16,.12SQ,20
Reach Compliance Code compliant compliant
series 8S 8S
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code S-XQCC-N16 S-XQCC-N16
JESD-609 code e3 e3
length 3 mm 3 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 3 3
Number of functions 1 1
Number of terminals 16 16
Actual output times 4 4
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code HQCCN HQCCN
Encapsulate equivalent code LCC16,.12SQ,20 LCC16,.12SQ,20
Package shape SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG CHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5/3.3 V 2.5/3.3 V
Prop。Delay @ Nom-Sup 0.32 ns 0.32 ns
propagation delay (tpd) 0.32 ns 0.32 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.025 ns 0.025 ns
Maximum seat height 1.05 mm 1.05 mm
Maximum supply voltage (Vsup) 2.625 V 2.625 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) - annealed
Terminal form NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 3 mm 3 mm

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