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74AUP1G08GX/S500H

Description
AUP/ULP/V SERIES, 2-INPUT AND GATE, PDSO5
Categorylogic    logic   
File Size179KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

74AUP1G08GX/S500H Overview

AUP/ULP/V SERIES, 2-INPUT AND GATE, PDSO5

74AUP1G08GX/S500H Parametric

Parameter NameAttribute value
MakerNXP
package instructionSON,
Reach Compliance Codeunknown
seriesAUP/ULP/V
JESD-30 codeS-PDSO-N5
length0.8 mm
Logic integrated circuit typeAND GATE
Number of functions1
Number of entries2
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Package shapeSQUARE
Package formSMALL OUTLINE
propagation delay (tpd)24 ns
Maximum seat height0.35 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formNO LEAD
Terminal pitch0.48 mm
Terminal locationDUAL
width0.8 mm
74AXP1G08
Low-power 2-input AND gate
Rev. 1 — 15 January 2014
Product data sheet
1. General description
The 74AXP1G08 is a single 2-input AND gate.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
V
CC
range from 0.7 V to 2.75 V. It is fully specified for partial power down applications
using I
OFF
. The I
OFF
circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; C
I
= 0.5 pF (typical)
Low output capacitance; C
O
= 1.0 pF (typical)
Low dynamic power consumption; C
PD
= 2.4 pF at V
CC
= 1.2 V (typical)
Low static power consumption; I
CC
= 0.6
A
(85
C
maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
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