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DPLS350E_15

Description
LOW VCE(SAT) PNP SURFACE MOUNT TRANSISTOR
File Size126KB,5 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
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DPLS350E_15 Overview

LOW VCE(SAT) PNP SURFACE MOUNT TRANSISTOR

DPLS350E
LOW V
CE(SAT)
PNP SURFACE MOUNT TRANSISTOR
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Features
Epitaxial Planar Die Construction
Ideally Suited for Automated Assembly Processes
Ideal for Medium Power Switching or Amplification Applications
Lead Free By Design/RoHS Compliant (Note 1)
"Green" Device (Note 2)
Mechanical Data
COLLECTOR
2,4
Case: SOT-223
Case Material: Molded Plastic, "Green” Molding Compound.
UL Flammability Classification Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020D
Terminals: Finish — Matte Tin annealed over Copper leadframe
(Lead Free Plating). Solderable per MIL-STD-202, Method 208
Marking Information: See Page 4
Ordering Information: See Page 4
Weight: 0.115 grams (approximate)
3 E
C 4
2 C
1 B
Pin Out Configuration
1
BASE
3
EMITTER
Top View
Device Schematic
Maximum Ratings
@T
A
= 25°C unless otherwise specified
Symbol
V
CBO
V
CEO
V
EBO
I
CM
I
C
I
B
Value
-60
-50
-6
-5
-3
-1
Unit
V
V
V
A
A
A
Characteristic
Collector-Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Peak Pulse Current
Continuous Collector Current
Base Current
Thermal Characteristics
Characteristic
Power Dissipation (Note 3) @ T
A
= 25°C
Thermal Resistance, Junction to Ambient Air (Note 3) @ T
A
= 25°C
Operating and Storage Temperature Range
Notes:
Symbol
P
D
R
θ
JA
T
J
, T
STG
Value
1
125
-55 to +150
Unit
W
°C/W
°C
1. No purposefully added lead.
2. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
3. Device mounted on FR-4 PCB; pad layout as shown on page 4 or in Diodes Inc. suggested pad layout document AP02001, which can
be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
DPLS350E
Document number: DS31230 Rev. 4 - 2
1 of 5
www.diodes.com
April 2009
© Diodes Incorporated

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