W3H128M72ER2-533SBI datasheet, PDF

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W3H128M72ER2-533SBI: DescriptionDDR DRAM, 128MX72, 0.5ns, CMOS, PBGA255, 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255; Categorystorage storage; File Size1MB，34 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W3H128M72ER2-533SBI Overview

DDR DRAM, 128MX72, 0.5ns, CMOS, PBGA255, 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255

W3H128M72ER2-533SBI Parametric

Parameter Name	Attribute value
Maker	White Electronic Designs Corporation
package instruction	BGA,
Reach Compliance Code	unknown
access mode	MULTI BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B255
length	23 mm
memory density	9663676416 bit
Memory IC Type	DDR DRAM
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	255
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128MX72
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm

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White Electronic Designs

W3H128M72ER-XNBX

PRELIMINARY*

128M x 72 REGISTERED DDR2 SDRAM 255 PBGA

FEATURES



Data rate = 667, 533, 400 Mb/s

Package:

• 255 Plastic Ball Grid Array (PBGA), 23 x 21mm

• 1.27mm pitch



Core Supply Voltage = 1.8V

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal

Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes

On Die Termination (ODT)

Adjustable data – output drive strength

Programmable CAS latency: 4, 5 or 6

CK/CK# Termination options available

• 0 ohm, 20 ohm



Posted CAS additive latency: 0, 1, 2, 3 or 4

Write latency = Read latency - 1* t

Commercial, Industrial and Military Temperature

Ranges

1GByte Organized as 128M x 72

Weight: W3H128M72ER-XNBX - 4 grams max

BENEFITS



45% Space savings vs. FBGA

Reduced part count

51% I/O reduction vs FBGA

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

* This product is under development, is not fully qualiﬁed or characterized and is

subject to change without notice.

FIGURE 1 – DENSITY COMPARISONS

CSP Approach (mm)

5.5

11.5

W3H128M72ER-XNBX

13.5

FBGA

14.0

FBGA

White Electronic Designs

W3H128M72ER-XSBX

45%

51%

Area

I/O

Count

5 x 161mm

+ 1 x 74mm

= 879mm

5 x 84 balls + 1 x 96 balls = 516 balls

483mm

255 Balls

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

February 2009

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

TABLE 1 – BALL DESCRIPTIONS

Symbol

ODT

Type

Input

W3H128M72ER-XNBX

PRELIMINARY

Description

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When

enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and

UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing

of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the

crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the

DDR2 SDRAM. The speciﬁc circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁguration

and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks

idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down

exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding

CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.

CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V

is applied during

ﬁ

rst power-up. After

REF

has become stable during the power on and initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper SELF-REFRESH operation, V

REF

must be maintained.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands

are masked when CS# is registered HIGH.

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled

HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM

loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for

upper byte DQ8–DQ15, of each of U0-U4

Bank address inputs: BA0–BA2 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is

being applied. BA0–BA2 deﬁne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the

LOAD MODE command.

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10

sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD

MODE command.

Data input/output: Bidirectional data bus

Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-

aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is

enabled via the LOAD MODE command.

Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-

aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is

enabled via the LOAD MODE command.

Power Supply: I/O + Core; V

CCQ

is common to V

SSTL_18 reference voltage.

Ground

No connect: These balls should be left unconnected.

Future use; address bits A14 and A15 are reserved for future densities. Address bits F1, F2, and G2 are reserved

for optional parity function

CK, CK#

Input

CKE

Input

CS#

RAS#, CAS#,

WE#

LDM, UDM

Input

BA0–BA2

Input

A0-A13

Input

DQ0-63

UDQS, UDQS#

I/O

LDQS, LDQS#

REF

DNU

I/O

Supply

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

February 2009

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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