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RTSX32SU-1CQ208B

Description
Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 310MHz, 2880-Cell, CMOS, CQFP208
CategoryProgrammable logic devices    Programmable logic   
File Size5MB,100 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

RTSX32SU-1CQ208B Overview

Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 310MHz, 2880-Cell, CMOS, CQFP208

RTSX32SU-1CQ208B Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
package instructionCERAMIC, QFP-208
Reach Compliance Codecompliant
Revision 9
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Designed for Space
• SEU-Hardened Registers Eliminate the Need to Implement
Triple-Module Redundancy (TMR)
– Immune to Single Event Upsets (SEU) to LET
th
> 40 MeV-
cm
2
/mg,
– SEU Rate < 10
–10
Upset/Bit-Day in Worst-Case
Geosynchronous Orbit
• Up to 100 krad (Si) Total Ionizing Dose (TID)
– Parametric Performance Supported with Lot-Specific Test
Data
• Single-Event Latch-Up (SEL) Immunity to LET
TH
> 104
MeVcm2/mg
• TM1019.5 Test Data Available
• QML Certified Devices
Specifications
0.25 µm Metal-to-Metal Antifuse Process (UMC)
48,000 to 108,000 Available System Gates
Up to 2,012 SEU-Hardened Flip-Flops
Up to 360 User-Programmable I/O Pins
Features
• Very Low Power Consumption (Up to 68 mW at Standby)
• 3.3 V and 5 V Mixed Voltage
• Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, TTL, and
CMOS
– 5 V Input Tolerance and 5 V Drive Strength
– Slow Slew Rate Option
– Configurable Weak Resistor Pull-Up/Down for Tristated
Outputs at Power-Up
– Hot-Swap Compliant with Cold-Sparing Support
• Secure Programming Technology Designed to Protect Against
Reverse Engineering and Design Theft
• 100% Circuit Resource Utilization with 100% Pin Locking
• Unique In-System Diagnostic and Verification Capability with
Silicon Explorer II
• Deterministic, User-Controllable Timing
• JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 – Dedicated JTAG Reset (TRST) Pin
High Performance
• 230 MHz System Performance
• 310 MHz Internal Performance
• 9.5 ns Input Clock to Output Pad
Processing Flows
• B-Flow – MIL-STD-883B
• E-Flow – Extended Flow
• EV-Flow – Class V Equivalent Flow Processing Consistent with
MIL-PRF 38535
Prototyping Options
• Commercial SX-A Devices for Functional Verification
• RTSX-SU PROTO Devices with Same Functional and Timing
Characteristics as Flight Unit in a Non-Hermetic Package
Table 1 • RTSX-SU Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
SEU-Hardened Register Cells (Dedicated Flip-Flops)
Maximum Flip-Flops
Maximum User I/Os
Clocks
Quadrant Clocks
Speed Grades
Package
(by pin count)
CQ
CG
CC
RTSX32SU
32,000
48,000
2,880
1,800
1,080
1,980
227
3
0
Std., –1
84, 208, 256
256
RTSX72SU
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Std., –1
208, 256
624
March 2012
© 2012 Microsemi Corporation
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