IDT74ALVC1G02
3.3V CMOS SINGLE 2-INPUT POSITIVE-NOR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS
SINGLE 2-INPUT
POSITIVE-NOR
GATE
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.65mm pitch PSOP package
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 1.65V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVC1G02:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
IDT74ALVC1G02
DESCRIPTION:
This single 2-input positive-NOR gate is built using advanced dual
metal CMOS technology. The ALVC1G02 is designed for 1.65V to 3.6V
V
CC
operation and performs the Boolean function Y = A + B or Y = A
·
B
in positive logic.
The ALVC1G02 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A
1
4
2
Y
A
B
GND
1
2
3
5
V
CC
B
SO5-1
4
Y
PSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
A, B
Y
Description
Data Inputs
Data Output
FUNCTION TABLE
(1)
Inputs
A
H
X
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
B
X
H
L
Output
Y
L
L
H
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4778/-
IDT74ALVC1G02
3.3V CMOS SINGLE 2-INPUT POSITIVE-NOR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
ALVC 1G Link
Max.
– 0.5 to + 4.6
–0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
C
I/O
°C
mA
mA
mA
mA
NOTE:
1. As applicable to the device type.
ALVC 1G Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C, V
CC
= 2.3V to 3.6V
Symbol
V
IH
Parameter
Input HIGH Voltage Level
V
CC
Test Conditions
= 1.65V to 1.95V
Min.
0.65 x V
CC
1.7
2
—
—
—
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
—
0.35 x V
CC
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
10
µA
µA
V
mV
µA
µA
V
Unit
V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
Input LOW Voltage Level
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
Quiescent Power Supply
Current Variation
—
—
750
µA
ALVC 1G Link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2
IDT74ALVC1G02
3.3V CMOS SINGLE 2-INPUT POSITIVE-NOR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 1.65V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
1.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
—
—
—
—
2
—
—
—
—
—
—
0.2
0.45
0.4
0.7
0.4
0.55
ALVC 1G Link
Max.
—
Unit
V
V
CC
= 1.65V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 1.65V to 3.6V
V
CC
= 1.65V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 1.8V ± 0.15V
Symbol
C
PD
Parameter
Power Dissipation Capacitance
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
V
CC
= 2.5V ± 0.2V
Typical
V
CC
= 3.3V ± 0.3V
Typical
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 1.8V ± 0.15V
Symbol
Parameter
t
PLH
Propagation Delay
A or B to Y
t
PHL
Min.
1
Max.
8
V
CC
= 2.5V ± 0.2V
Min.
1
Max.
3.8
V
CC
= 2.7V
Min.
Max.
3.6
V
CC
= 3.3V ± 0.3V
Min.
1
Max.
3.2
Unit
ns
NOTE:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
3
IDT74ALVC1G02
3.3V CMOS SINGLE 2-INPUT POSITIVE-NOR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ± 0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ± 0.2V Unit
2 x Vcc
V
Vcc
Vcc / 2
150
150
30
V
V
mV
mV
pF
ALVC 1G Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW IT CH
NORMALLY
C LO SE D
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LO AD/2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LO AD/2
V
LZ
V
OL
V
OH
V
HZ
0V
ALVC 1G Link
V
LO AD
Open
GND
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
DEFINITIONS:
ALVC 1G Link
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIM ING
INPUT
t
R EM
ASYNCHRONOUS
CONTROL
ALVC 1G Link
t
S U
t
H
GND
Open
SYNCHRONOUS
CONTROL
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC 1G Link
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALVC 1G Link
V
T
4
IDT74ALVC1G02
3.3V CMOS SINGLE 2-INPUT POSITIVE-NOR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
1.8V
±
0.15V TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 1.8V ± 0.15V
2 x V
CC
V
CC
V
CC
/ 2
150
150
30
Unit
V
V
V
mV
mV
pF
ALVC 1G Link
SAME PHASE
IN P U T T R A N S IT IO N
t
P L H
OUTPUT
t
P L H
O P P O S IT E P H A S E
IN P U T T R A N S IT IO N
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
A L V C 1 G L in k
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
LOAD
O p en
1 00 0
Ω
P u lse
G e ne ra to r
(1 )
ENABLE AND DISABLE TIMES
ENABLE
C O N TR O L
IN P U T
t
PZ L
O U TPU T
S W IT C H
N O R M ALLY
CLO SED
LOW
t
P Z H
OUTPUT
S W IT C H
N O R M A L LY
OPEN
H IG H
V
L O A D /2
V
T
t
PH Z
V
T
0V
t
P L Z
D IS A B L E
V
IH
V
T
0V
V
L O A D /2
V
LZ
V
OL
V
OH
V
HZ
0V
A L V C 1 G L in k
GND
V
IN
D .U .T .
V
OUT
R
T
C
L
1000
Ω
DEFINITIONS:
A L V C 1 G L in k
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTE:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
D ATA
IN P U T
T IM IN G
IN P U T
t
R EM
ASYNCHRONO US
C O N TR O L
ALVC 1G Link
t
S U
t
H
GND
Open
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
A L V C 1 G L in k
SYNCHRONOUS
C O N TR O L
t
S U
t
H
PULSE WIDTH
L O W -H IG H -LO W
P U LS E
t
W
H IG H -L O W -H IG H
P U LS E
V
T
A L V C 1 G L in k
V
T
5
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