RH80536GE0462M datasheet, PDF - EEWORLD Datasheet

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RH80536GE0462M: Description2130 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，65 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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RH80536GE0462M Overview

2130 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478

RH80536GE0462M Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
Parts packaging code	PGA
package instruction	SPGA,
Contacts	478
Reach Compliance Code	unknown
Address bus width	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P478
length	35 mm
low power mode	YES
Number of terminals	478
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
Certification status	COMMERCIAL
Maximum seat height	3.27 mm
speed	2130 MHz
Maximum supply voltage	1.37 V
Minimum supply voltage	1.25 V
surface mount	NO
Terminal surface	NOT SPECIFIED
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® Pentium® M Processor with 2-MB L2 cache and 533-MHz Front Side Bus may contain design defects or errors known as errata which may

cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

∆

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families. See www.intel.com/products/processor_number for details

Intel, Pentium, and Intel SpeedStep, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the

United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

1.1

1.2

2.1

Introduction.................................................................................................................................... 7

Terminology .................................................................................................................................. 8

References ................................................................................................................................... 9

Low Power Features.................................................................................................................... 11

Clock Control and Low Power States ......................................................................................... 11

2.1.1 Normal State.................................................................................................................. 11

2.1.2 AutoHALT Powerdown State ......................................................................................... 11

2.1.3 Stop-Grant State............................................................................................................ 12

2.1.4 HALT/Grant Snoop State............................................................................................... 12

2.1.5 Sleep State .................................................................................................................... 12

2.1.6 Deep Sleep State...........................................................................................................13

2.1.7 Deeper Sleep State ....................................................................................................... 13

Enhanced Intel SpeedStep

Technology ................................................................................... 14

FSB Low Power Enhancements ................................................................................................. 15

Processor Power Status Indicator (PSI#) Signal ........................................................................ 15

Electrical Specifications ............................................................................................................. 17

Power and Ground Pins.............................................................................................................. 17

FSB Clock (BCLK[1:0]) and Processor Clocking ........................................................................ 17

Voltage Identification .................................................................................................................. 17

Catastrophic Thermal Protection ................................................................................................ 18

Signal Terminations and Unused Pins........................................................................................ 19

FSB Frequency Select Signals (BSEL[1:0]) ............................................................................... 19

FSB Signal Groups ..................................................................................................................... 19

CMOS Signals ............................................................................................................................ 20

Maximum Ratings ....................................................................................................................... 21

Processor DC Specifications ...................................................................................................... 21

Package Mechanical Specifications and Pin Information ....................................................... 27

Processor Pinout and Pin List..................................................................................................... 35

Alphabetical Signals Reference.................................................................................................. 51

Thermal Specifications and Design Considerations................................................................ 59

Thermal Specifications ............................................................................................................... 61

5.1.1 Thermal Diode ............................................................................................................... 61

5.1.2 Thermal Diode Offset..................................................................................................... 61

5.1.3 Intel

Thermal Monitor................................................................................................... 62

2.2

2.3

2.4

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

4.1

4.2

5.1

Datasheet

Figures

2-1

3-1

3-2

4-1

4-2

4-3

4-4

4-5

4-6

4-7

Clock Control States................................................................................................................11

Active VCC and ICC Load Line ...............................................................................................23

Deep Sleep VCC and ICC Load Line ......................................................................................24

Micro-FCPGA Package Top and Bottom Isometric Views ......................................................27

Micro-FCPGA Package - Top and Side Views ........................................................................28

Micro-FCPGA Package - Bottom View ....................................................................................29

Micro-FCBGA Package Top and Bottom Isometric View ........................................................31

Micro-FCBGA Package Top and Side Views ..........................................................................32

Micro-FCBGA Package Bottom View ......................................................................................34

The Coordinates of the Processor Pins As Viewed from the Top of the Package ..................35

Tables

1-1

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

4-1

4-2

4-3

4-4

4-5

5-1

5-2

5-3

References ................................................................................................................................ 9

Voltage Identification Definition ............................................................................................... 18

BSEL[1:0] Encoding for BCLK Frequency............................................................................... 19

FSB Pin Groups....................................................................................................................... 20

Processor DC Absolute Maximum Ratings ............................................................................. 21

Voltage and Current Specifications ......................................................................................... 22

FSB Differential BCLK Specifications ...................................................................................... 24

AGTL+ Signal Group DC Specifications.................................................................................. 25

CMOS Signal Group DC Specifications .................................................................................. 25

Open Drain Signal Group DC Specifications ........................................................................... 26

Micro-FCPGA Package Dimensions ....................................................................................... 30

Micro-FCBGA Package Dimensions ....................................................................................... 33

Pin Listing by Pin Name .......................................................................................................... 37

Pin Listing by Pin Number ....................................................................................................... 43

Signal Description.................................................................................................................... 51

Power Specifications for Intel

Pentium

M Processor........................................................... 60

Thermal Diode Interface .......................................................................................................... 61

Thermal Diode Specifications .................................................................................................. 62

Datasheet

RH80536GE0462M Related Products

	RH80536GE0462M	RH80536GE0512M	RH80536GE0362M	RH80536GE0302M
Description	2130 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478	2260 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478	1860 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478	1730 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	PGA	PGA	PGA	PGA
package instruction	SPGA,	SPGA,	SPGA,	SPGA,
Contacts	478	478	478	478
Reach Compliance Code	unknown	unknown	unknown	unknow
Address bus width	32	32	32	32
boundary scan	YES	YES	YES	YES
maximum clock frequency	133 MHz	133 MHz	133 MHz	133 MHz
External data bus width	64	64	64	64
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES	YES
JESD-30 code	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478
length	35 mm	35 mm	35 mm	35 mm
low power mode	YES	YES	YES	YES
Number of terminals	478	478	478	478
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA	SPGA	SPGA	SPGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	3.27 mm	3.27 mm	3.27 mm	3.27 mm
speed	2130 MHz	2260 MHz	1860 MHz	1730 MHz
Maximum supply voltage	1.37 V	1.4 V	1.35 V	1.35 V
Minimum supply voltage	1.25 V	1.25 V	1.25 V	1.25 V
surface mount	NO	NO	NO	NO
Terminal surface	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	35 mm	35 mm	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR

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