AN4104
Application note
Using the STM32F0xx DMA controller
Introduction
This application note describes how to use the STM32F0xx direct memory access (DMA)
controller. The STM32F0xx DMA controller, the Cortex™-M0 core, the advanced
microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a
high data bandwidth and to develop very-low latency response time software.
This application note also describes how to take full advantage of these features and ensure
correct response times for different peripherals and subsystems.
Note:
To ensure a quick start, application cases presented in this document are implemented in C
language and are available in Project\STM32F0xx_StdPeriph_Examples within the
STM32F0xx_StdPeriph_Lib package.
May 2012
Doc ID 023131 Rev 1
1/13
www.st.com
Contents
AN4104
Contents
1
DMA controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
DMA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DMA Data managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1
1.2.2
1.2.3
1.2.4
Round robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Peripheral to Memory, Memory to Peripheral and Peripheral to Peripheral
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory to Memory DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Choosing channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3
DMA Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
DMA firmware driver API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
How to use DMA Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
DMA programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
ADC DMA transfer to TIM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DMA Flash to RAM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DMA RAM to DAC example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI DMA example: communication between two SPIs using DMA . . . . . 11
USART communication boards data exchange using DMA example . . . 11
4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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DMA controller description
1
DMA controller description
Direct memory access (DMA) is used in order to provide high-speed data transfer
betweenperipherals and memory as well as memory to memory. Data can be quickly moved
by DMA without any CPU actions. This keeps CPU resources free for other operations.
The DMA allows data transfers to take place in the background, without the intervention of
the Cortex-M0 processor. During this operation, the main processor can execute other tasks
and it is only interrupted when a whole data block is available for processing. Large amounts
of data can be transferred with no major impact on the system performance.
The DMA is mainly used to implement central data buffer storage (usually in system SRAM)
for different peripheral modules. This solution is less expensive in terms of silicon and power
consumption compared to a distributed solution where each peripheral needs to implement
its own local data storage.
Depending on the sales type used, one or two DMA controllers are implemented
.
The STM32F0xx DMA controller has 5 channels for DMA1 in total, each dedicated to
manage memory access requests from one or more peripherals. It has an arbiter for
handling the priority between DMA requests.
1.1
DMA Overview
The DMA(s) offer(s):
●
●
●
independently configurable channels (requests)
Each channels are connected to dedicated hardware DMA requests, software trigger is
also supported on each channel
Priorities between requests from channels of one DMA are software programmable (4
levels: very high, high, medium, low) or hardware in case of equality (request 1 has
priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. The source and the address must have the same data size (to
be aligned on the data size).
Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
Memory-to-memory transfer
Peripheral-to-memory and memory-to-peripheral as well as peripheral-to-peripheral
transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536
●
●
●
●
●
●
●
The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually
located in system SRAM.
Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals
connected to the same DMA channel (CH1 to CH5 in
Table 1
for STM32F0xx devices)
cannot be used simultaneously with active DMA (DMA function active in the peripheral
register).
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DMA controller description
AN4104
The different peripherals supporting DMA transfers in STM32F0xx devices are shown in
Table 1.
Table 1.
Peripherals served by DMA1 and channel allocation
Peripherals
ADC
ADC1
SPI1
SPI
SPI2
USART1
USART
USART2
I
2
C1
I
2
C2
TIM1
TIM2
TIM3
TIM6/DAC
TIM
TIM15
TIM2_CH3
TIM1_CH1
TIM2_UP
TIM3_CH3
TIM1_CH2
TIM2_CH2
TIM3_CH4
TIM3_UP
TIM6_UP
DAC
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
TIM16_CH1
TIM16_UP
TIM17_CH1
TIM17_UP
TIM17_CH1
TIM17_UP
TIM16_CH1
TIM16_UP
I2C1_TX
I2C1_RX
I2C2_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM2_CH4
TIM3_CH1
TIM3_TRIG
I2C2_RX
TIM1_UP
TIM1_CH3
TIM2_CH1
USART2_
TX
USART2_RX
USART1_
TX
USART1_RX
SPI2_RX
USART1_
TX
SPI2_TX
USART1_RX
CH1
ADC1
CH2
ADC1
SPI1_RX
SPI1_TX
CH3
CH4
CH5
I
2
C
TIM16
TIM17
Note:
For more details,refer to RM0091 DMA section for STM32F0xx devices.
1.2
DMA Data managing
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M0 core. When the CPU and DMA are targeting the same destination (memory or
peripheral) the DMA request may stop the CPU access to the system bus for several bus
cycles. The bus matrix implements round-robin scheduling, thus ensuring at least half of the
system bus bandwidth (both to memory and peripheral) for the CPU.
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DMA controller description
1.2.1
Round robin priority scheme
The NVIC and Cortex-M0 processor implement a high-performance very low latency
interrupt scheme. All Cortex-M0 instructions are either executed in a single cycle or are
interruptible at cycle level. In order to preserve this advantage at system level, the DMA and
bus matrix ensure that the DMA does not block the bus for a long time. The round-robin
priority scheme ensures that the CPU can access any slave buses during every second
cycle, if needed.
1.2.2
Peripheral to Memory, Memory to Peripheral and Peripheral to
Peripheral DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
releases the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
Each DMA transfer consists of three operations:
●
The loading of data from the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address.
The storage of the data loaded to the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address.
The post-decrementing of the DMA counter, which contains the number of transactions
that still have to be performed.
●
●
1.2.3
Memory to Memory DMA transactions
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode. If the MEM2MEM bit is set, then the channel
initiates transfers as soon as it is enabled by software by setting the Enable bit.
The transfer stops once the DMA counter reaches zero. Memory to Memory mode may not
be used at the same time as Circular mode.
1.2.4
Choosing channel priority
In order to achieve continuous data transfers to/from a peripheral, the corresponding DMA
channel must be able to sustain the peripheral data rate and ensure that the service latency
is shorter than the period of time between two consecutive data.
The high speed/high bandwidth peripherals must have the highest DMA priorities. This
ensures that the maximum data latency will be respected for these peripherals and
over/under-run conditions will be avoided.
In case of equal bandwidth requirements, it is recommended to assign a higher priority to
the peripherals working in slave mode (which have no control on the data transfer speed)
compared with the ones working in master mode (which may control the data flow).
Doc ID 023131 Rev 1
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