FTS256S8N-12I datasheet, PDF - EEWORLD Datasheet

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FTS256S8N-12I: DescriptionStandard SRAM, 256KX8, 120ns, CMOS, CDIP32, CERAMIC, SIDE BRAZED, DIP-32; Categorystorage storage; File Size341KB，6 Pages; ManufacturerForce Technologies Ltd.

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FTS256S8N-12I Overview

Standard SRAM, 256KX8, 120ns, CMOS, CDIP32, CERAMIC, SIDE BRAZED, DIP-32

FTS256S8N-12I Parametric

Parameter Name	Attribute value
Maker	Force Technologies Ltd.
Parts packaging code	DIP
package instruction	DIP,
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	120 ns
JESD-30 code	R-CDIP-T32
length	42.164 mm
memory density	2097152 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	10.16 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm

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2 Megabit CMOS SRAM

DESCRIPTION:

The FTS256S8N is a Military 256K X 8 high-density,

low-power static RAM module comprised of two

ceramic 128K X 8 monolithic SRAM’s, an advanced

high-speed CMOS decoder and decoupling capacitors

surface mounted on a co-fired ceramic substrate

having side-brazed leads.

The FTS256S8N is available in a 600-mil-wide, 32-pin

dual-in-line package that conforms to the same JEDEC

standard pin configuration as the future four megabit

monolithics.

The FTS256S8N operates from a single +5V supply

and all input and output pins are completely

TTL-compatible. The low standby power of the

FTS256S8N make it ideal for battery-backed

applications.

FTS256S8N

FEATURES:

•

262,144 by 8 bit configuration

•

Access Times: 85*, 100, 120, 150ns

- Faster Speeds Upon Request

•

Low Power Dissipation:

µW

(typ.) standby

375 mW (typ.) operating

•

2-Volt data retention

•

Fully Static Operation - No clock or refresh

required

•

All inputs and outputs are TTL-compatible

•

600 mil, 32-pin JEDEC standard DIP pinout

Commercial Only.

PIN NAMES

A0 - A17

Address Inputs

I/O0 - I/O7

Data In/Out

Chip Enable

Write Enable

Output Enable

Power (+5V)

Ground

N.C.

No Connect

PIN-OUT DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

This document contains information on a product that is currently released

to production at FORCE Technologies. FORCE reserves the right to

change products or specifications herein without prior notice.

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