QL3025 / QL3025R
25,000 Usable PLD Gate pASIC 3 FPGA
Combining High Performance
and
High Density
PRELIMINARY DATA
pASIC 3
HIGHLIGHTS
March, 1998
®
2
High Performance and High Density
-25,000 Usable PLD Gates with 204 I/Os
-16-bit counter speeds over 250 MHz, data path speeds over 275 MHz
-0.35µm four-layer metal non-volatile CMOS process for smallest die sizes
pASIC 3
… 25,000
usable PLD gates,
204 I/O pins
Easy to Use / Fast Development Cycles
-100% routable with 100% utilization and complete pin-out stability
-Variable-grain logic cells provide high performance and 100% utilization
-Comprehensive design tools include high quality Verilog/VHDL synthesis
16,128 bit RAM
Option
High Speed Embedded SRAM Available in “R” Versions
-14 dual-port RAM modules, organized in user-configurable 1,152-bit blocks
-5ns access times, each port independently accessible
-Fast and efficient for FIFO, RAM, and ROM functions
Advanced I/O Capabilities
-Interfaces with both 3.3 volt and 5.0 volt devices
-PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades
-Full JTAG boundary scan
-Registered I/O cells with individually controlled clocks and output enables
QL3025
Block Diagram
672
Logic
Cells
2-27
QL3025 / QL3025R
PRODUCT
SUMMARY
The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of
FPGAs. pASIC 3 FPGAs are fabricated on a 0.35µm four-layer metal process
using QuickLogic’s patented ViaLink technology to provide a unique
combination of high performance, high density, low cost, and extreme ease-of-
use.
The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the
QL3025 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA
packages. The QL3025R also includes 14 dual port RAM modules, each with
1,152 bits, for a total of 16,128 RAM bits.
Software support for the complete pASIC 3 family, including the QL3025, is
available through three basic packages. The turnkey QuickWorks
®
package
provides the most complete FPGA software solution from design entry to logic
synthesis, to place and route, to simulation.
The QuickChip
TM
and
QuickTools
TM
packages provide a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 204 I/O Pins
- 196 bidirectional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew Distributed Networks
- Two array clock/control networks available to the logic cell flip-flop
clock, set and reset inputs - each driven by an input-only pin
- Two global clock/control networks available to the logic cell F1, clock,
set and reset inputs and the input and I/O register clock, reset and enable
inputs as well as the output enable control - each driven by an input-only
or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output total delays under 6 ns
- Data path speeds exceeding 275 MHz
- Counter speeds over 250 MHz
2-28
QL3025 / QL3025R
PINOUT DIAGRAMS
PIN # 109
PIN # 1
144-PIN TQFP
2
pASIC 3
pASIC
QL3025-1PF144C
PIN # 73
PIN # 37
208-PIN PQFP
PIN # 1
PIN # 157
pASIC
QL3025-1PQ208C
PIN # 53
2-29
PIN # 105
QL3025 / QL3025R
PQFP 208 and TQFP 144 Pinout Table
208
144 Function 208
144 Function 208
144 Function 208
144 Function 208
144
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
1
2
3
NC
4
5
NC
6
7
NC
NC
8
NC
9
NC
10
11
12
13
NC
14
15
16
17
18
19
20
21
22
23
NC
24
NC
25
NC
26
27
28
NC
NC
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
30
31
NC
32
NC
33
NC
34
35
36
37
38
39
NC
40
NC
NC
41
42
43
NC
44
45
NC
46
47
48
NC
49
NC
50
51
52
NC
53
54
55
56
NC
57
58
59
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
I/O
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
60
61
NC
62
63
NC
NC
64
NC
65
66
67
NC
NC
68
69
NC
70
71
72
NC
73
NC
74
75
76
77
NC
78
79
80
NC
81
82
NC
83
NC
84
85
NC
86
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
87
88
89
90
91
92
93
94
95
NC
96
NC
97
98
NC
99
NC
100
NC
101
102
103
104
NC
105
106
NC
107
NC
108
109
110
111
NC
112
113
NC
NC
114
115
116
NC
GND
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
STM
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
117
118
119
120
NC
NC
121
NC
122
123
124
NC
125
126
127
128
129
NC
130
131
132
NC
133
134
NC
135
136
NC
137
NC
138
139
NC
140
NC
141
142
NC
143
144
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TDO
I/O
2-30
QL3025 / QL3025R
PINOUT DIAGRAM
256-PIN PBGA
2
pASIC 3
pASIC
QL3025-1PB256C
TOP
PIN A1
CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 18 16 14 12
10 8
6
4
19 17 15 13 11
9
7
5
3
2
1
BOTTOM
2-31
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