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HM64YGB36100 Series
32M Synchronous Late Write Fast Static RAM
(1-Mword
×
36-bit)
REJ03C0271-0100
(Previous ADE-203-1374 (Z) Rev. 0.0)
Rev.1.00
Jun.27.2005
Description
The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword
×
36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V
±
5% operation and 1.5 V (V
DDQ
)
32-Mbit density
Synchronous register to register operation
Internal self-timed late write
Byte write control (4 byte write selects, one for each 9-bit)
Optional
×18
configuration
HSTL compatible I/O
Programmable impedance output drivers
Differential HSTL clock inputs
Asynchronous
G
output control
Asynchronous sleep mode
FC-BGA 119pin package with SRAM JEDEC standard pinout
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Ordering Information
Type No.
HM64YGB36100BP-33
Organization
1M
×
36
Access time
1.6 ns
Cycle time
3.3 ns
Package
119-bump 1.27 mm
14 mm
×
22 mm BGA
PRBG0119DC-A (BP-119F)
Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: V
DD
= 2.5 V, G: Late Write SRAM, B: V
DDQ
= 1.5 V
Rev.1.00 Jun 27, 2005 page 1 of 19
HM64YGB36100 Series
Pin Descriptions
Name
V
DD
V
SS
V
DDQ
V
REF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
M1, M2
TMS
TCK
TDI
TDO
NC
M1
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Output
M2
Descriptions
Core power supply
Ground
Output power supply
Input reference, provides input reference voltage
Clock input, active high
Clock input, active low
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n: 1 to 20
x: a to d
1
x: a to d
n: 0 to 8
Protocol
Notes
V
SS
V
DD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to V
SS
via a resistance RQ where 175
Ω ≤
RQ
≤
300
Ω.
If ZQ = V
DDQ
or open, output
buffer impedance will be maximum.
2. Mode control input pins M1 and M2 are set at power-up and will not change the states during the SRAM
operates.
This SRAM supports only single clock, pipelined read protocol.
Other settings are not applicable.
Mode control pin M2 can be set to V
DDQ
instead of V
DD
.
Rev.1.00 Jun 27, 2005 page 3 of 19
ARM Technology
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