Datasheet
μ
PD44165084B
μ
PD44165094B
μ
PD44165184B
μ
PD44165364B
18M-BIT QDR II SRAM
4-WORD BURST OPERATION
Description
TM
R10DS0018EJ0200
Rev.2.00
October 6, 2011
The
μ
PD44165084B is a 2,097,152-word by 8-bit, the
μ
PD44165094B is a 2,097,152-word by 9-bit, the
μ
PD44165184B is a 1,048,576-word by 18-bit and the
μ
PD44165364B is a 524,288-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell.
The
μ
PD44165084B,
μ
PD44165094B,
μ
PD44165184B and
μ
PD44165364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require synchronous
operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-
pin PLASTIC BGA.
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports with concurrent transactions
•
100% bus utilization DDR READ and WRITE operation
•
Four-tick burst for reduced address frequency
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 1 of 39
μ
PD44165084B,
μ
PD44165094B
, μ
PD44165184B,
μ
PD44165364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44165084B]
2M x 8
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NW1#
NC/288M
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
NW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D7
Q0 to Q7
R#
W#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb.
2A and 10A of this product can also be used as NC.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 4 of 39
μ
PD44165084B,
μ
PD44165094B
, μ
PD44165184B,
μ
PD44165364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44165094B]
2M x 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC/288M
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D8
Q0 to Q8
R#
W#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb.
2A and 10A of this product can also be used as NC
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 5 of 39
MCU
京公网安备 11010802033920号
EEWORLD
