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UM0434 Overview

The primary objective of this userâs manual is to describe

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UM0434

e200z3 PowerPC core

Reference

manual

Introduction

The primary objective of this user’s manual is to describe the functionality of the e200z3

embedded microprocessor core for software and hardware developers. This book is

intended as a companion to the

EREF: A Programmer's Reference Manual for Freescale

Book E Processors

(hereafter referred to as

EREF).

Book E is a PowerPC™ architecture definition for embedded processors that ensures binary

compatibility with the user-instruction set architecture (UISA) portion of the PowerPC

architecture as it was jointly developed by Apple, IBM, and Motorola (referred to as the AIM

architecture).

This document distinguishes among the three levels of the architectural and implementation

definition, as follows:

●

The Book E architecture—Book E defines a set of user-level instructions and registers

that are drawn from the user instruction set architecture (UISA) portion of the AIM

definition PowerPC architecture. Book E also includes numerous supervisor-level

registers and instructions as they were defined in the AIM version of the PowerPC

architecture for the virtual environment architecture (VEA) and the operating

environment architecture (OEA).

Because the operating system resources (such as the MMU and interrupts) defined by

Book E differ greatly from those defined by the AIM architecture, Book E introduces

many new registers and instructions.

●

Freescale Book E implementation standards (EIS)—In many cases, the Book E

architecture definition provides a general framework, leaving specific details up to the

implementation. To ensure consistency among its Book E implementations, Freescale

has defined implementation standards that provide an additional layer of architecture

between Book E and the actual devices.

e200z3 implementation details—Each processor typically defines instructions,

registers, register fields, and other aspects that are more detailed than either the

Book E definition or the EIS. This book describes all of the instructions and registers

implemented on the e200z3, including those defined by Book E and by the EIS, as well

as those that are e200z3-specific.

●

Information in this book is subject to change without notice, as described in the disclaimers

on the title page of this book. As with any technical documentation, it is the readers’

responsibility to be sure they are using the most recent version of the documentation.

Nov 2013

Rev

1/391

www.st.com

Table of contents

UM0434

Table of contents

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.1

1.2

1.3

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.1

2.2

Terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

e200z3 core complex overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1

3.2

3.3

3.4

3.5

Overview of the e200z3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.1

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

VLE APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.5.1

3.5.2

3.5.3

3.5.4

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.6

Microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6.1

3.6.2

3.6.3

3.6.4

3.6.5

3.6.6

Instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Load/Store unit (LSU) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Memory management unit (MMU) features . . . . . . . . . . . . . . . . . . . . . . 34

System bus (core complex interface) features . . . . . . . . . . . . . . . . . . . . 35

Nexus3 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.7

Legacy support of PowerPC architecture . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.7.1

3.7.2

3.7.3

3.7.4

Instruction set compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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UM0434

3.7.5

3.7.6

Table of contents

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1

4.2

4.3

4.4

PowerPC Book E registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

e200z3 - Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

e200z3-Specific Device Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 43

Processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4.1

4.4.2

4.4.3

4.4.4

Machine state register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Processor ID register (PIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Processor version register (PVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

System version register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.5

Registers for integer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.5.1

4.5.2

General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Integer exception register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6

Registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.1

4.6.2

4.6.3

Condition register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Count register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Link register (LR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.7

SPE and SPFP APU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.7.1

4.7.2

Signal processing/embedded floating-point status and control

Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.8

4.9

Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.8.1

Interrupt Registers Defined by Book E . . . . . . . . . . . . . . . . . . . . . . . . . 56

Exception syndrome register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.9.1

4.9.2

4.9.3

4.9.4

VLE mode instruction syndrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Misaligned instruction fetch syndrome . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Precise external termination error syndrome . . . . . . . . . . . . . . . . . . . . . 61

e200z3 specific interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.10

4.11

Software use SPRs (SPRG0–SPRG7 and USPRG0) . . . . . . . . . . . . . . . 63

Timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.11.1

4.11.2

4.11.3

4.11.4

Timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Timer status register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Time base (TBU and TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Decrementer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3/391

Table of contents

4.11.5

UM0434

Decrementer auto-reload register (DECAR) . . . . . . . . . . . . . . . . . . . . . 69

4.12

Debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.12.1

4.12.2

4.12.3

4.12.4

Debug address and value registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Debug counter register (DBCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Debug control and status registers (DBCR0–DBCR3) . . . . . . . . . . . . . 71

Debug status register (DBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.13

Hardware implementation dependent registers . . . . . . . . . . . . . . . . . . . . 84

4.13.1

4.13.2

Hardware implementation dependent register 0 (HID0) . . . . . . . . . . . . 84

Hardware implementation dependent register 1 (HID1) . . . . . . . . . . . . 86

4.14

4.15

4.16

Branch target buffer (BTB) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.14.1

Branch unit control and status register (BUCSR) . . . . . . . . . . . . . . . . . 87

L1 cache configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.15.1

L1 cache configuration register 0 (L1CFG0) . . . . . . . . . . . . . . . . . . . . . 88

MMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.16.1

4.16.2

4.16.3

4.16.4

4.16.5

MMU control and status register 0 (MMUCSR0) . . . . . . . . . . . . . . . . . . 88

MMU configuration register (MMUCFG) . . . . . . . . . . . . . . . . . . . . . . . . 89

TLB configuration registers (TLBnCFG) . . . . . . . . . . . . . . . . . . . . . . . . 90

MMU assist registers (MAS0–MAS4, MAS6) . . . . . . . . . . . . . . . . . . . . 91

Process ID register (PID0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.17

4.18

Support for fast context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.17.1

Context control register (CTXCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

SPR register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.18.1

4.18.2

4.18.3

4.18.4

Invalid SPR references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Synchronization requirements for SPRs . . . . . . . . . . . . . . . . . . . . . . . . 98

Special purpose register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Reset settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.19

Parallel signature unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.19.1

4.19.2

4.19.3

4.19.4

4.19.5

4.19.6

4.19.7

Parallel signature control register (PSCR) . . . . . . . . . . . . . . . . . . . . . . 104

Parallel signature status register (PSSR) . . . . . . . . . . . . . . . . . . . . . . 105

Parallel signature high register (PSHR) . . . . . . . . . . . . . . . . . . . . . . . . 105

Parallel signature low register (PSLR) . . . . . . . . . . . . . . . . . . . . . . . . . 106

Parallel signature counter register (PSCTR) . . . . . . . . . . . . . . . . . . . . 106

Parallel signature update high register (PSUHR) . . . . . . . . . . . . . . . . 106

Parallel signature update low register (PSULR) . . . . . . . . . . . . . . . . . 107

Instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4/391

UM0434

Table of contents

5.1

Operand conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.1.1

5.1.2

5.1.3

Data organization in memory and data transfers . . . . . . . . . . . . . . . . . 108

Alignment and misaligned accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 108

e200z3 Floating-Point implementation . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

Unsupported instructions and instruction forms . . . . . . . . . . . . . . . . . . . 109

Optionally supported instructions and instruction forms . . . . . . . . . . . . 109

Implementation-Specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

BookE instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Memory access alignment support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Memory synchronization and reservation instructions . . . . . . . . . . . . . . 111

Branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Interruption of instructions by interrupt requests . . . . . . . . . . . . . . . . . . 112

e200z3-Specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.10.1

5.10.2

5.10.3

5.10.4

Integer select APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Debug APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

SPE APU instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Embedded vector and scalar single precision floating point APU

instructions 120

5.11

5.12

5.13

Unimplemented SPRs and read only SPRs . . . . . . . . . . . . . . . . . . . . . . 122

Invalid instruction forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.13.1

5.13.2

Instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . 123

Instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Interrupts and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

6.1

6.2

6.3

6.4

6.5

6.6

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

e200z3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Exception syndrome register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Machine state register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.4.1

Machine check syndrome register (MCSR) . . . . . . . . . . . . . . . . . . . . . 166

Interrupt vector offset registers (IVORn) . . . . . . . . . . . . . . . . . . . . . . . . . 167

Interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.6.1

6.6.2

6.6.3

Critical input interrupt (IVOR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Machine check interrupt (IVOR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Data storage interrupt (IVOR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5/391

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