V437464S24V
3.3 VOLT 64M x 72 HIGH PERFORMANCE
UNBUFFERED ECC SDRAM MODULE
PRELIMINARY
s
168 Pin Unbuffered ECC 67,108,864 x 72 bit
Oganization SDRAM Modules
s
Utilizes High Performance 32M x 8 SDRAM in
TSOPII-54 Packages
s
Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
s
Single +3.3V (± 0.3V) Power Supply
s
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
s
Auto Refresh (CBR) and Self Refresh
s
All Inputs, Outputs are LVTTL Compatible
s
8192 Refresh Cycles every 64 ms
s
Serial Present Detect (SPD)
s
Speed
Grade
-75PC, CL=2,3
(133 MHz)
-75, CL=3
(133 MHz)
-10PC, CL=2,3
(100 MHz)
CILETIV LESOM
Features
Part Number
V437464S24VXTG-75PC
V437464S24VXTG-75
V437464S24VXTG-10PC
V437464S24V Rev. 1.0 January 2002
Description
The V437464S24V memory module is organized
67,108,864 x 72 bits in a 168 pin dual in line
memory module (DIMM). The 64M x 72 unbuffered
DIMM uses 18 Mosel-Vitelic 32M x 8 ECC SDRAM.
The x72 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
Configuration
64M x 72
64M x 72
64M x 72
1
V437464S24V
Front
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
CILETIV LESOM
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin Configurations (Front Side/Back Side)
Notes:
*
These pins are not used in this module.
Pin Names
A0–A12
I/O1–I/O64
RAS
CAS
WE
BA0, BA1
CKE0, CKE1
CS0–CS3
CLK0–CLK3
DQM0–DQM7
VCC
VSS
SCL
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Bank Selects
Clock Enable
Chip Select
Clock Input
Data Mask
Power (+3.3 Volts)
Ground
Clock for Presence Detect
CB0–CB7
NC
DU
SA0–A2
SDA
Serial Data OUT for Presence
Detect
Serial Data IN for Presence
Detect
Check Bits (x72 Organization)
No Connection
Don’t Use
V437464S24V Rev. 1.0 January 2002
2
V437464S24V
Block Diagram
CS1
CS0
DQM0
I/O1–I/O8
10Ω
DQM1
I/O9–I/O16
10Ω
(BC7:0)
DQM CS
I/O1–I/O8 D16
DQM CS
I/O1–I/O8 D17
DQM5
I/O41–I/O48
DQM CS
I/O1–I/O8 D1
DQM CS
I/O1–I/O8 D9
DQM5
I/O41–I/O48
10Ω
DQM CS
I/O1–I/O8 D0
DQM CS
I/O1–I/O8 D8
DQM4
I/O33–I/O40
10Ω
DQM CS
I/O1–I/O8 D5
DQM CS
I/O1–I/O8 D13
DQM CS
I/O1–I/O8 D4
DQM CS
I/O1–I/O8 D12
CILETIV LESOM
V
MOSEL VITELIC
MANUFACTURED
Module Part Number Information
4
3
74
64
S
2
4
V
X
X
G - XX
SPEED
75PC = PC133 CL3,2
75 = PC133 CL3
10PC = PC133 CL3,2
LEAD FINISH
G = GOLD
SDRAM
3.3V
WIDTH
DEPTH
168 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
COMPONENT
PACKAGE, T = TSOP
COMPONENT A=0.17u B=0.14u
REV LEVEL
LVTTL
4 BANKS
CS3
CS2
DQM2
I/O17–I/O24
10Ω
DQM3
I/O25–I/O32
10Ω
E
2
PROM SPD (256 WORD X 8 BIT)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
SDA
V
DD
WP
47K
CS
DQM
I/O1–I/O8 D2
CS
DQM
I/O1–I/O8 D3
CS
DQM
I/O1–I/O8 D10
CS
DQM
I/O1–I/O8 D11
DQM6
I/O49–I/O56
10Ω
DQM7
I/O57–I/O64
10Ω
CS
DQM
I/O1–I/O8 D6
CS
DQM
I/O1–I/O8 D7
CS
DQM
I/O1–I/O8 D14
CS
DQM
I/O1–I/O8 D15
A11-A0, BA0, BA1
D0-D15 (D16, D17)
D0-D15 (D16, D17)
C0-C31, (C32...C35)
C33-C42
D0-D15 (D16, D17)
D0-D15 (D16, D17)
D0-D7 (D16)
V
CC
10K
V
SS
RAS, CAS, WE
CKE0
CLOCK WIRING
32M X 72
CLK0
CLK1
CLK2
CLK3
5 SDRAM
5 SDRAM
4 SDRAM +3.3pF
4 SDRAM +3.3pF
CKE1
D9-D15 (D17)
V437464S24V Rev. 1.0 January 2002
3
V437464S24V
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
A serial presence detect storage device –
2
PROM – is assembled onto the module. Informa-
E
tion about the module configuration, speed, etc. is
CILETIV LESOM
SPD-Table :
0
1
2
3
4
Memory Type
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CS Latencies
WE Latencies
24
25
26
27
V437464S24V Rev. 1.0 January 2002
Serial Presence Detect Information
Byte Num-
ber
Function Described
Number of SPD bytes
Total bytes in Serial PD
Hex Value
SPD Entry Value
128
256
SDRAM
13
10
-75PC
80
08
04
0D
0A
-75
80
08
04
0D
0A
-10PC
80
08
04
0D
0A
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8
SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
2
72
0
LVTTL
7.5 ns/10.0 ns
5.4 ns/6.0 ns
ECC
Self-Refresh, 7.8µs
x8
n/a / x8
t
ccd
= 1 CLK
1, 2, 4, 8
4
CL = 3, 2
CS Latency = 0
WL = 0
Non Buffered/Non Reg.
Vcc tol ± 10%
7.5 ns/10.0 ns
02
48
00
01
75
54
02
82
08
08
01
02
48
00
01
A0
60
02
82
08
08
01
02
48
00
01
A0
60
02
82
08
08
01
0F
04
06
01
01
00
0E
75
0F
04
06
01
01
00
0E
A0
0F
04
06
01
01
00
0E
A0
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency
=2
Maximum Data Access Time from Clock for
CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL = 1
Minimum Row Precharge Time
5.4 ns/6.0 ns
54
60
60
Not Supported
Not Supported
00
00
00
00
00
00
15 ns /20 ns
0F
14
14
4
V437464S24V
CILETIV LESOM
28
29
30
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
SPD Revision
Reserved
Reserved
SPD-Table : (Continued)
Byte Num-
ber
Function Described
Minimum Row Active to Row Active Delay
t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Fu-
ture)
Revision 2/1.2
Hex Value
SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0E
-75
0F
-10PC
10
15 ns/20 ns
42 ns/45 ns
256 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
0F
2A
40
15
08
15
08
00
14
2D
40
15
08
15
08
00
14
2D
40
20
10
20
10
00
02
10
02
8C
40
00
12
C3
40
00
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
V437464S24V
Mosel Vitelic
40
00
00
64
00
00
00
64
00
00
00
64
00
00
Intel Specification for Frequency
Unused Storage Location
DC Characteristics
T
A
= 0°C to 70°C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
Limit Values
Symbol
V
IH
V
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (I
OUT
= –4.0 mA)
Min.
2.0
–0.5
2.4
Max.
V
CC
+0.3
0.8
—
Unit
V
V
V
V437464S24V Rev. 1.0 January 2002
5
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