Data Sheet
FEATURES
74.25 MHz 16-/24-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
Six 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (F
SC
) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Dual data rate (DDR) input support
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7342 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7342 only)
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
Serial MPU interface with I
2
C compatibility
3.3 V analog operation, 1.8 V digital operation, and 1.8 V or
3.3 V I/O operation
Temperature range: −40°C to +85°C
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Rev.
D
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADV7342/ADV7343
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Revision History ............................................................................... 4
General Description ......................................................................... 5
Functional Block Diagram .............................................................. 6
Specifications..................................................................................... 7
Power Supply and Voltage Specifications .................................. 7
Voltage Reference Specifications ................................................ 7
Input Clock Specifications .......................................................... 7
Analog Output Specifications ..................................................... 8
Digital Input/Output Specifications—3.3 V ............................. 8
Digital Input/Output Specifications—1.8 V ............................. 8
Digital Timing Specifications—3.3 V ........................................ 9
Digital Timing Specifications—1.8 V ...................................... 10
MPU Port Timing Specifications ............................................. 11
Power Specifications .................................................................. 11
Video Performance Specifications ........................................... 12
Timing Diagrams ............................................................................ 13
Absolute Maximum Ratings.......................................................... 20
Thermal Resistance .................................................................... 20
ESD Caution ................................................................................ 20
Pin Configuration and Function Descriptions ........................... 21
Typical Performance Characteristics ........................................... 23
MPU Port Description ................................................................... 28
I
2
C Operation .............................................................................. 28
Register Map Access ....................................................................... 30
Register Programming ............................................................... 30
Subaddress Register (SR7 to SR0) ............................................ 30
Input Configuration ....................................................................... 48
Standard Definition Only .......................................................... 48
Enhanced Definition/High Definition Only .......................... 49
Simultaneous Standard Definition and Enhanced
Definition/High Definition ....................................................... 49
Enhanced Definition Only (at 54 MHz) ................................. 50
Output Configuration .................................................................... 51
Design Features ............................................................................... 52
Output Oversampling ................................................................ 52
HD Interlace External P_HSYNC and P_VSYNC
Considerations ............................................................................ 53
ED/HD Timing Reset ................................................................ 53
Data Sheet
SD Subcarrier Frequency Lock ................................................. 53
SD VCR FF/RW Sync ................................................................ 54
Vertical Blanking Interval ......................................................... 54
SD Subcarrier Frequency Control ............................................ 54
SD Noninterlaced Mode ............................................................ 54
SD Square Pixel Mode ............................................................... 55
Filters............................................................................................ 56
ED/HD Test Pattern Color Controls ....................................... 57
Color Space Conversion Matrix ............................................... 57
SD Luma and Color Scale Control ........................................... 59
SD Hue Adjust Control.............................................................. 59
SD Brightness Detect ................................................................. 59
SD Brightness Control ............................................................... 59
SD Input Standard Autodetection ............................................ 60
Double Buffering ........................................................................ 61
Programmable DAC Gain Control .......................................... 61
Gamma Correction .................................................................... 61
ED/HD Sharpness Filter and Adaptive Filter Controls ......... 63
ED/HD Sharpness Filter and Adaptive Filter Application
Examples ...................................................................................... 64
SD Digital Noise Reduction ...................................................... 65
SD Active Video Edge Control ................................................. 66
External Horizontal and Vertical Synchronization Control . 68
Low Power Mode ........................................................................ 69
Cable Detection .......................................................................... 69
DAC Autopower-Down ............................................................. 69
Sleep Mode .................................................................................. 70
Pixel and Control Port Readback ............................................. 70
Reset Mechanism........................................................................ 70
SD Teletext Insertion ................................................................. 70
Printed Circuit Board Layout and Design .................................. 72
Unused Pins ................................................................................ 72
DAC Configurations .................................................................. 72
Voltage Reference ....................................................................... 72
Video Output Buffer and Optional Output Filter .................. 72
Printed Circuit Board (PCB) Layout ....................................... 73
Typical Application Circuit ....................................................... 75
Copy Generation Management System ....................................... 76
SD CGMS .................................................................................... 76
ED CGMS .................................................................................... 76
Rev.
D
| Page 2 of 108
Data Sheet
HD CGMS ....................................................................................76
CGMS CRC Functionality .........................................................76
SD Wide Screen Signaling ..............................................................79
SD Closed Captioning ....................................................................80
Internal Test Pattern Generation ...................................................81
SD Test Patterns ...........................................................................81
ED/HD Test Patterns ..................................................................81
SD Timing ........................................................................................82
HD Timing .......................................................................................87
Video Output Levels .......................................................................88
SD YPrPb Output Levels—SMPTE/EBU N10 ........................88
ADV7342/ADV7343
ED/HD YPrPb Output Levels ................................................... 89
SD/ED/HD RGB Output Levels ................................................ 90
SD Output Plots .......................................................................... 91
Video Standards .............................................................................. 92
Configuration Scripts ..................................................................... 94
Standard Definition .................................................................... 94
Enhanced Definition .................................................................. 98
High Definition .........................................................................101
Outline Dimensions ......................................................................106
Ordering Guide .........................................................................106
Rev.
D
| Page 3 of 108
ADV7342/ADV7343
REVISION HISTORY
3/12—Rev. C to Rev. D
Changed ADV7340/ADV7341 to ADV7342/ADV7343 ........... 70
3/12—Rev. B to Rev. C
Reorganized Layout ............................................................ Universal
Change to Features Section ............................................................. 1
Moved Revision History Section .................................................... 4
Change to Table 1 ............................................................................. 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 15 ........................................................................ 21
Changes to Table 21 ........................................................................ 33
Changes to Table 24 ........................................................................ 36
Changes to Table 29 ........................................................................ 41
Changes to Table 30 ........................................................................ 42
Changes to 24-Bit 4:4:4 RGB Mode Section ............................... 48
Deleted ED/HD Nonstandard Timing Mode Section, Figure 59,
and Table 42, Renumbered Sequentially ..................................... 50
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode
Section, and Figure 60 .................................................................... 51
Deleted Figure 61 ............................................................................ 52
Added External Sync Polarity Section ......................................... 52
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section .................................................................................... 53
Changes to ED/HD Test Patterns Section ................................... 81
9/11—Rev. A to Rev. B
Changes to MPU Port Description Section ................................ 27
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1 .......................................................................... 5
Changes to Table 6 ............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions ......................................................................... 10
Deleted Figure 20 ............................................................................ 18
Changes to Table 13 ........................................................................ 19
Data Sheet
Changes to Table 15 ....................................................................... 20
Changes to MPU Port Description Section ................................ 27
Changes to I
2
C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Added Figure 49 ............................................................................. 28
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 29
Changes to Table 21, 0x30 Bit Description ................................. 32
Changes to Table 29 ....................................................................... 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31, 0xA0 Register Name ................................. 42
Changes to Table 32 ....................................................................... 43
Added Table 33 and Table 34 ........................................................ 44
Changes to Standard Definition Only Section ........................... 46
Added Figure 52 ............................................................................. 47
Changes to Figure 53...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58 ......................... 48
Renamed Features Section to Design Features Section............. 50
Changes to ED/HD Nonstandard Timing Mode Section ......... 50
Changes to Figure 60...................................................................... 51
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section .................................................................. 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section .................................................. 51
Changes to Programming the F
SC
Section................................... 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 53
Changes to Subaddress 0x82, Bit 4 Section ................................. 53
Added SD Manual CSC Matrix Adjust Feature Section ............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 57
Changes to SD Brightness Detect Section................................... 58
Changes to Figure 71...................................................................... 60
Added Sleep Mode Section ........................................................... 68
Changes to Pixel and Control Port Readback Section .............. 68
Added SD Teletext Insertion Section ........................................... 68
Added Unused Pins Section .......................................................... 70
Added Figure 86 and Figure 87 .................................................... 70
Changes to Power Supply Sequencing Section ........................... 72
Changes to Figure 94...................................................................... 75
Changes to SD Wide Screen Signaling Section .......................... 77
Changes to Internal Test Pattern Generation Section ............... 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section .................................. 80
Added Configuration Scripts Section .......................................... 92
10/06—Revision 0: Initial Version
Rev. D | Page 4 of 108
Data Sheet
GENERAL DESCRIPTION
The ADV7342/ADV7343 are high speed, digital-to-analog
video encoders in a 64-lead LQFP package. Six high speed,
3.3 V, 11-bit video DACs provide support for composite
(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog
outputs in standard definition (SD), enhanced definition (ED),
or high definition (HD) video formats.
The ADV7342/ADV7343 have a 24-bit pixel input port that can
be configured in a variety of ways. SD video formats are sup-
ported over an SDR interface, and ED/HD video formats are
supported over SDR and DDR interfaces. Pixel data can be
supplied in either the YCrCb or RGB color spaces.
The parts also support embedded EAV/SAV timing codes,
external video synchronization signals, and I
2
C® communication
protocol.
In addition, simultaneous SD and ED/HD input and output are
supported. Full-drive DACs ensure that external output buffering
is not required, while 216 MHz (SD and ED) and 297 MHz
(HD) oversampling ensures that external output filtering is not
required.
Cable detection and DAC autopower-down features keep power
consumption to a minimum.
Table 1 lists the video standards directly supported by the
ADV7342/ADV7343.
ADV7342/ADV7343
Table 1. Standards Directly Supported by the ADV7342/
ADV7343
Active
Resolution
720 × 240
720 × 288
720 × 480
720 × 576
640 × 480
768 × 576
720 × 483
720 × 483
720 × 483
720 × 576
720 × 483
720 × 576
1920 × 1035
1920 × 1035
1280 × 720
1280 × 720
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1
I/P
P
P
I
I
I
I
P
P
P
P
P
P
I
I
P
P
I
I
P
P
P
1
Frame
Rate (Hz)
59.94
50
29.97
25
29.97
25
59.94
59.94
59.94
50
59.94
50
30
29.97
60, 50, 30,
25, 24
23.97,
59.94, 29.97
30, 25
29.97
30, 25, 24
23.98, 29.97
24
Clock Input
(MHz)
27
27
27
27
24.54
29.5
27
27
27
27
27
27
74.25
74.1758
74.25
74.1758
74.25
74.1758
74.25
74.1758
74.25
Standard
ITU-R
BT.601/656
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
SMPTE 293M
BTA T-1004
ITU-R BT.1358
ITU-R BT.1358
ITU-R BT.1362
ITU-R BT.1362
SMPTE 240M
SMPTE 240M
SMPTE 296M
SMPTE 296M
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
ITU-R BT.709-5
I = interlaced, P = progressive.
Rev.
D
| Page 5 of 108
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