Multiformat SDTV Video Decoder
ADV7181B
FEATURES
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™),
signal processing, and enhanced FIFO management
give mini-TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision
®
copy protection detection
Chroma transient improvement (CTI)
Digital noise reduction (DNR)
Multiple programmable analog input formats
Composite video (CVBS)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for
close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
VBI decode support for
close captioning, WSS, CGMS, EDTV, and
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I
2
C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package and 64-lead LFCSP package
GENERAL DESCRIPTION
The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-bit/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
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The six analog input channels accept standard composite,
S-Video, and YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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APPLICATIONS
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DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receivers
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I
2
C-compatible).
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181B is available in two packages, a small 64-lead
LQFP Pb-free package and a 64-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADV7181B
TABLE OF CONTENTS
Introduction ...................................................................................... 4
Analog Front End ......................................................................... 4
Standard Definition Processor ................................................... 4
Functional Block Diagram .............................................................. 5
Specifications..................................................................................... 6
Electrical Characteristics............................................................. 6
Video Specifications..................................................................... 7
Timing Specifications .................................................................. 8
Analog Specifications................................................................... 8
Thermal Specifications ................................................................ 9
Timing Diagrams.......................................................................... 9
Absolute Maximum Ratings.......................................................... 10
General Setup.............................................................................. 20
Color Controls ............................................................................ 22
Clamp Operation........................................................................ 24
Luma Filter .................................................................................. 25
Chroma Filter.............................................................................. 28
Gain Operation........................................................................... 29
Digital Noise Reduction (DNR) ............................................... 33
Comb Filters................................................................................ 33
AV Code Insertion and Controls ............................................. 36
Synchronization Output Signals............................................... 38
Sync Processing .......................................................................... 46
VBI Data Decode ....................................................................... 46
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Analog Front End ........................................................................... 13
Analog Input Muxing ................................................................ 13
Global Control Registers ............................................................... 15
Power-Save Modes...................................................................... 15
Reset Control .............................................................................. 15
B
Global Pin Control ..................................................................... 16
Global Status Registers................................................................... 18
Identification............................................................................... 18
Status 1 ......................................................................................... 18
Autodetection Result.................................................................. 18
Status 2 ......................................................................................... 18
Status 3 ......................................................................................... 18
Standard Definition Processor (SDP).......................................... 19
SD Luma Path ............................................................................. 19
SD Chroma Path......................................................................... 19
Sync Processing........................................................................... 20
VBI Data Recovery..................................................................... 20
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Rev. B | Page 2 of 100
Pixel Port Configuration ............................................................... 59
MPU Port Description................................................................... 60
Register Accesses ........................................................................ 61
Register Programming............................................................... 61
I
2
C Sequencer.............................................................................. 61
I
2
C Register Maps ........................................................................... 62
I
2
C Register Map Details ........................................................... 67
I
2
C Programming Examples.......................................................... 88
Examples for 28 MHz Clock..................................................... 88
Examples for 27 MHz Clock..................................................... 92
PCB Layout Recommendations.................................................... 95
Analog Interface Inputs ............................................................. 95
Power Supply Decoupling ......................................................... 95
PLL ............................................................................................... 95
Digital Outputs (Both Data and Clocks) ................................ 95
Digital Inputs .............................................................................. 96
Antialiasing Filters ..................................................................... 96
Crystal Load Capacitor Value Selection.................................. 96
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Chroma Transient Improvement (CTI) .................................. 32
ADV7181B
Typical Circuit Connection ...........................................................97
Outline Dimensions........................................................................99
REVISION HISTORY
Ordering Guide .........................................................................100
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Rev. B | Page 3 of 100
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7/05—Rev. 0 to Rev. A
Changed Crystal References to 28 MHz Crystal............ Universal
Changes to General Description Section .......................................1
Changes to Analog Specifications Section.....................................8
Changes to Clamp Operation Section ..........................................24
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7/04—Revision 0: Initial Version
9/05—Rev. A to Rev. B
Changes to Table 1 ............................................................................6
Changes to Table 2 ............................................................................7
Changes to Table 3 and Table 4 .......................................................8
Changes to Table 5 ............................................................................9
Changes to Figure 5.........................................................................13
Changes to Figure 7.........................................................................19
Changes to Lock Related Controls Section..................................21
Changes to Table References in BETACAM Section..................31
Changes to PAL Comb Filter Settings Section ............................34
Changes to Figure 20 ......................................................................40
Change to NFTOG Section............................................................43
Changes to Table 84 ........................................................................67
Changes to Table 85 ........................................................................72
Changes to Figure 11 to Figure 14 ................................................28
Changes to Description of Chroma Filter....................................28
Changes to Figure 15 ......................................................................29
Changes to Luma Gain LAGC[2:0] Bits Address........................30
Changes to VSEHE VS End Horizontal Position Section..........39
Changes to Table 54 ........................................................................41
Changes to Table 55 ........................................................................42
Changes to Table 83 ........................................................................67
Changes to Table 84 ........................................................................71
Changes to Table 85 ........................................................................88
Changes to Table 86 ........................................................................89
Changes to Table 87 ........................................................................90
Changes to Table 88 ........................................................................91
Added XTAL Load Capacitor Value Selection Section..............96
Replaced Figure 45..........................................................................98
ADV7181B
INTRODUCTION
The ADV7181B is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked,
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc,
NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The
ADV7181B can automatically detect the video standard and
process it accordingly.
The ADV7181B has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standards and signal quality with no user intervention required.
Video user controls, such as brightness, contrast, saturation,
and hue, are also available within the ADV7181B.
The ADV7181B implements a patented ADLLT algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7181B to track and decode poor
quality video sources such as VCRs, noisy sources from tuner
outputs, VCD players, and camcorders. The ADV7181B
contains a chroma transient improvement (CTI) processor that
sharpens the edge rate of chroma transitions, resulting in
sharper vertical transitions.
The ADV7181B can process a variety of VBI data services such
as close captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7181B is
fully Macrovision certified; detection circuitry enables Type I,
Type II, and Type III protection levels to be identified and
reported to the user. The decoder is also fully robust to all
Macrovision signal inputs.
ANALOG FRONT END
The ADV7181B analog front end comprises three 9-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end uses
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181B. Current
and voltage clamps are positioned in front of each ADC to
ensure the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7181B.
The ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR
The ADV7181B is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported by the ADV7181B
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Rev. B | Page 4 of 100
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6
A/D
9
LUMA
FILTER
GAIN
CONTROL
LUMA
RESAMPLE
DATA
PREPROCESSOR
9
LUMA
2D COMB
(4H MAX)
9
A/D
9
A/D
DECIMATION AND
DOWNSAMPLING
FILTERS
AIN1–
AIN6
CLAMP
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9
STANDARD DEFINITION PROCESSOR
LUMA
DIGITAL
FINE
CLAMP
8
8
L-DNR
PIXEL
DATA
CVBS
S-VIDEO
YPrPb
INPUT
MUX
CLAMP
FUNCTIONAL BLOCK DIAGRAM
CLAMP
B
SYNC AND
CLK CONTROL
SYNC
EXTRACT
LINE
LENGTH
PREDICTOR
RESAMPLE
CONTROL
AV
CODE
INSERTION
16
HS
VS
CTI
C-DNR
SYNC PROCESSING AND
CLOCK GENERATION
SO
F
SC
RECOVERY
CHROMA
DIGITAL
FINE
CLAMP
CHROMA
DEMOD
CHROMA
FILTER
GAIN
CONTROL
CHROMA
RESAMPLE
CHROMA
2D COMB
(4H MAX)
OUTPUT FORMATTER
Figure 1.
Rev. B | Page 5 of 100
FIELD
ADV7181B
LLC
SFL
CONTROL
AND DATA
INTRQ
VBI DATA RECOVERY
GLOBAL CONTROL
SYNTHESIZED
LLC CONTROL
SCLK
SDA
ALSB
SERIAL INTERFACE
CONTROL AND VBI DATA
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MACROVISION
DETECTION
STANDARD
AUTODETECTION
FREE RUN
OUTPUT CONTROL
04984-001
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ADV7181B
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