Changes to Ordering Guide .......................................................... 24
1/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD9859
AD9859—ELECTRICAL SPECIFICATIONS
Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R
SET
= 3.92 kΩ, External Reference Clock Frequency =
20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled at 4×
REFCLK Multiplier Enabled at 20×
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power
1
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz A
OUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband SFDR
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
Temp
Min
Typ
Max
Unit
FULL
FULL
FULL
25°C
25°C
25°C
25°C
FULL
1
20
4
3
1.5
50
35
–15
0
10
10
400
100
20
65
+3
MHz
MHz
MHz
pF
kΩ
%
%
dBm
Bits
mA
%FS
µA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
5
–10
15
+10
0.6
1
2
5
–105
–115
–132
AVDD – 0.5
64
63
61
55
50
82
82
94
87
82
84
87
87
80
82
86
89
80
82
84
86
AVDD + 0.5
Rev. A | Page 3 of 24
AD9859
Parameter
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
Minimum Data Setup Time DVDD_I/O = 1.8 V
Minimum Data Hold Time
Maximum Data Valid Time
Wake-Up Time
2
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION
4
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution
5
1
Temp
Min
Typ
Max
Unit
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25
7
7
2
3
5
0
25
1
5
4
6
0
24
24
16
1.25
0.6
2.2
3
2
1.35
0.4
2.8
0.4
162
150
20
62.5
100
±1
171
160
27
0.8
12
12
Mbps
ns
ns
ns
ns
ns
ns
ns
ms
SYSCLK Cycles
3
ns
ns
ns
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
MHz
MHz
SYSCLK Cycles
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
2
Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9859 section). The longest time required is for the
reference clock multiplier PLL to relock to the reference. The wake-up time assumes that there is no capacitor on DACBP and that the recommended PLL loop filter
values are used.
3
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
4
SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
5
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. A | Page 4 of 24
AD9859
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Maximum Junction Temperature
DVDD_I/O (Pin 43)
AVDD, DVDD
Digital Input Voltage (DVDD_I/O = 3.3 V)
Digital Input Voltage (DVDD_I/O = 1.8 V)
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (10 sec Soldering)
θ
JA
θ
JC
Rating
150°C
4V
2V
–0.7 V to +5.25 V
–0.7 V to +2.2 V
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
38°C/W
15°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
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