Data Sheet
FEATURES
25 MHz speed
On-chip SIN lookup table
On-chip, 10-bit DAC
Serial loading
Power-down option
Temperature range: −40°C to +85°C
200 mW power consumption
16-Lead TSSOP
25 MHz Direct Digital Synthesizer,
Waveform Generator
AD9832
GENERAL DESCRIPTION
The AD9832 is a numerically controlled oscillator employing
a phase accumulator, a sine look-up table, and a 10-bit digital-
to-analog converter (DAC) integrated on a single CMOS chip.
Modulation capabilities are provided for phase modulation and
frequency modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy can
be controlled to one part in 4 billion. Modulation is effected by
loading registers through the serial interface.
A power-down bit allows the user to power down the AD9832
when it is not in use, the power consumption being reduced to
5 mW (5 V) or 3 mW (3 V). The part is available in a 16-lead
TSSOP package.
Similar DDS products can be found at
www.analog.com/DDS.
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
FUNCTIONAL BLOCK DIAGRAM
DVDD
FSELECT
BIT
SELSRC
DGND
AVDD
AGND
REFOUT
FS ADJUST
REFIN
MCLK
FSELECT
MUX
ON-BOARD
REFERENCE
SYNC
FULL-SCALE
CONTROL
COMP
FREQ0 REG
FREQ1 REG
PHASE
ACCUMULATO
R
(32 BIT)
MUX
12
SIN
ROM
10-BIT DAC
IOUT
PHASE0 REG
PHASE1 REG
PHASE2 REG
SYNC
PHASE3 REG
SYNC
16-BIT DATA REGISTER
SYNC
8 MSBs
8 LSBs
DEFER REGISTER
SELSRC
CONTROL REGISTER
DECODE LOGIC
FSELECT/PSEL REGISTER
SERIAL REGISTER
09090-001
MUX
AD9832
MUX
MUX
PSEL0
BIT
PSEL1
BIT
FSYNC
SCLK
SDATA
PSEL0 PSEL1
Figure 1.
Rev. E
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AD9832
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
Circuit Description ......................................................................... 13
Numerical Controlled Oscillator and Phase Modulator ....... 13
Sine Look-Up Table (LUT)........................................................ 13
Digital-to-Analog Converter .................................................... 13
Functional Description .................................................................. 14
Serial Interface ............................................................................ 14
Direct Data Transfer and Deferred Data Transfer ................. 14
Data Sheet
Latency ......................................................................................... 16
Flowcharts ................................................................................... 16
Applications Information .............................................................. 19
Grounding and Layout .............................................................. 19
Interfacing the AD9832 to Microprocessors .............................. 19
AD9832 to ADSP-2101 Interface ............................................. 19
AD9832 to 68HC11/68L11 Interface ....................................... 20
AD9832 to 80C51/80L51 Interface .......................................... 20
AD9832 to DSP56002 Interface ............................................... 20
Evaluation Board ............................................................................ 21
System Demonstration Platform .............................................. 21
AD9832 to SPORT Interface ..................................................... 21
XO vs. External Clock................................................................ 21
Power Supply............................................................................... 21
Evaluation Board Schematics ................................................... 22
Evaluation Board Layout ........................................................... 24
Ordering Information .................................................................... 25
Bill of Materials ........................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
2/13—Rev. D to Rev. E
Changes to Table 10 ........................................................................ 15
Changes to Flowcharts Section ..................................................... 16
7/12—Rev. C to Rev. D
Changed On-Chip COS Lookup Table to On-Chip SIN Lookup
Table in Features Section ................................................................. 1
9/11—Rev. B to Rev. C
Changes to Features and Applications ........................................... 1
Changes to Specification Statement ............................................... 3
Changes to Timing Characteristics Statement ............................. 5
Replaced Evaluation Board Section; Renumbered
Sequentially ..................................................................................... 21
Changes to Ordering Guide .......................................................... 26
6/10—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changed CMOS Complete DDS to 3 V to 5.0 V Programmable
Waveform Generator.........................................................................1
Changes to Serial Interface Section.............................................. 14
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/99—Rev 0 to Rev. A
Rev. E | Page 2 of 28
Data Sheet
SPECIFICATIONS
AD9832
V
DD
= +5 V ± 5%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; REFIN = REFOUT; R
SET
= 3.9 kΩ; R
LOAD
= 300 Ω for IOUT, unless otherwise
noted. Also, see Figure 2.
Table 1.
Parameter
1
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (f
MAX
)
IOUT Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR)
3
Narrow Band (±50 kHz)
Wideband (±2 MHz)
Clock Feedthrough
Wake-Up Time
4
Power-Down Option
VOLTAGE REFERENCE
Internal Reference @ 25°C
T
MIN
to T
MAX
REFIN Input Impedance
Reference Temperature Coefficient (TC)
REFOUT Output Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
Input Capacitance, C
IN
POWER SUPPLIES
AVDD
DVDD
I
AA
I
DD
I
AA
+ I
DD 5
Low Power Sleep Mode
1
2
AD9832B
10
25
4
4.5
1.35
±1
±0.5
Unit
Bits
MSPS nom
mA nom
mA max
V max
LSB typ
LSB typ
Test Conditions/Comments
3 V power supply
50
−53
−72
−70
−50
−60
1
Yes
1.21
1.21 ± 7%
10
100
300
V
DD
− 0.9
0.9
10
10
2.97/5.5
2.97/5.5
5
2.5 + 0.4/MHz
15
24
350
dB min
dBc max
dBc min
dBc min
dBc min
dBc typ
ms typ
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
5 V power supply
3 V power supply
V typ
V min/V max
MΩ typ
ppm/°C typ
Ω typ
V min
V max
µA max
pF max
V min/V max
V min/V max
mA max
mA typ
mA max
mA max
µA max
5 V power supply
5 V power supply
3 V power supply
5 V power supply
Operating temperature range is −40°C to +85°C.
100% production tested.
3
f
MCLK
= 6.25 MHz, frequency word = 0x5671C71C, and f
OUT
= 2.11 MHz.
4
See Figure 13. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD. The AD9832 is tested with a capacitive load of 50 pF. The part can operate with higher capacitive
loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal is attenuated by 3 dB when the load capacitance equals 85 pF.
Rev. E | Page 3 of 28
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