Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Excluding Reference
Typically
±
0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
At dc and AV
DD
= 5 V
At dc and AV
DD
= 10 V
For Filter Notches of 10, 25, 50 Hz,
±
0.02
¥
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
¥
f
NOTCH
For Filter Notches of 10, 25, 50 Hz,
±
0.02
¥
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
¥
f
NOTCH
Parameter
STATIC PERFORMANCE
No Missing Codes
A, S Versions
1
24
22
18
15
12
See Tables I and II
±
0.0015
0.003
1
0.3
0.5
0.25
0.5
0.25
2
±
0.003
±
0.006
1
0.3
100
90
V
SS
to AV
DD
100
100
150
150
10
1
20
0 to +V
REF10
±
V
REF
See Table III
2.5 to 5
f
CLK IN
/256
2.5
±
1
20
30
1
1.5
1
Unit
Bits min
Bits min
Bits min
Bits min
Bits min
% FSR max
% FSR max
mV/∞C
typ
mV/∞C
typ
mV/∞C
typ
mV/∞C
typ
mV/∞C
typ
mV/∞C
typ
ppm/∞C typ
% FSR max
% FSR max
mV/∞C
typ
mV/∞C
typ
dB min
dB min
V min to V max
dB min
dB min
dB min
dB min
pA max
nA max
pF max
Output Noise
Integral Nonlinearity @ 25∞C
T
MIN
to T
MAX
Positive Full-Scale Error
2, 3, 4
Full-Scale Drift
5
Unipolar Offset Error
2, 4
Unipolar Offset Drift
5
Bipolar Zero Error
2, 4
Bipolar Zero Drift
5
Gain Drift
Bipolar Negative Full-Scale Error
2
@ 25∞C
Bipolar Negative Full-Scale Drift
5
T
MIN
to T
MAX
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Rejection (CMR)
Common-Mode Voltage Range
6
Normal-Mode 50 Hz Rejection
7
Normal-Mode 60 Hz Rejection
7
Common-Mode 50 Hz Rejection
7
Common-Mode 60 Hz Rejection
7
DC Input Leakage Current
7
@ 25∞C
T
MIN
to T
MAX
Sampling Capacitance
7
Analog Inputs
8
Input Voltage Range
9
nom
nom
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
Input Sampling Rate, f
S
Reference Inputs
REF IN(+) – REF IN(–) Voltage
11
Input Sampling Rate, f
S
REFERENCE OUTPUT
Output Voltage
Initial Tolerance @ 25∞C
Drift
Output Noise
Line Regulation (AV
DD
)
Load Regulation
External Current
V min to V max
For Specified Performance. Part Functions with
Lower V
REF
Voltages
V nom
% max
ppm/∞C typ
mV
typ
mV/V max
mV/mA max
mA max
pk-pk Noise 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
NOTES
1
Temperature ranges are as follows: A Version, –40∞C to +85∞C; S Version, –55∞C to +125∞C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20
mV
typical when using self-
calibration or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
7
These numbers are guaranteed by design and/or characterization.
8
The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
–2–
REV. D
AD7711A
Parameter
V
BIAS
INPUT
Input Voltage Range
12
A, S Versions
1
AV
DD
– 0.85
¥
V
REF
or AV
DD
– 3.5
or AV
DD
– 2.1
V
SS
+ 0.85
¥
V
REF
or V
SS
+ 3
Unit
Conditions/Comments
See V
BIAS
Input Section
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Smaller: +5 V/0 V Nominal AV
DD
/V
SS
See V
BIAS
Input Section
Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Greater: +5 V/0 V Nominal AV
DD
/V
SS
Increasing with Gain
V max
V max
V min
V min
dB typ
mA
max
V max
V min
V max
V min
V max
V min
mA
max
pF typ
mA
nom
% typ
%/∞C typ
mA
nom
% max
ppm/∞C typ
nA/V max
nA/V max
V max
V max
V max
V max
V min
V max
V
BIAS
Rejection
LOGIC INPUTS
Input Current
All Inputs except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
TRANSDUCER BURNOUT
Current
Initial Tolerance @ 25∞C
Drift
RTD EXCITATION CURRENT
Output Current
Initial Tolerance @ 25∞C
Drift
Line Regulation (AV
DD
)
Load Regulation
Output Compliance
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
Negative Full-Scale Calibration Limit
14
Offset Calibration Limit
15
Input Span
15
or V
SS
+ 2.1
65 to 85
±
10
0.8
2.0
0.8
3.5
0.4
DV
DD
– 1
±
10
9
4.5
±
10
0.1
400
±
20
20
400
400
AV
DD
– 2
(1.05
¥
V
REF
)/GAIN
–(1.05
¥
V
REF
)/GAIN
–(1.05
¥
V
REF
)/GAIN
0.8
¥
V
REF
/GAIN
(2.1
¥
V
REF
)/GAIN
I
SINK
= 1.6 mA
I
SOURCE
= 100
mA
AV
DD
= 5 V
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12
The AD7711A is tested with the following V
BIAS
voltages. With AV
DD
= 5 V and V
SS
= 0 V, V
BIAS
= 2.5 V, with AV
DD
= 10 V and V
SS
= 0 V, V
BIAS
= 5 V, and with
AV
DD
= 5 V and V
SS
= –5 V, V
BIAS
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. D
–3–
AD7711A–SPECIFICATIONS
Parameter
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
16
DV
DD
Voltage
17
AV
DD
–V
SS
Voltage
Power Supply Currents
AV
DD
Current
DV
DD
Current
V
SS
Current
Power Supply Rejection
18
Positive Supply (AV
DD
and DV
DD
)
19
Negative Supply (V
SS
)
Power Dissipation
Normal Mode
Normal Mode
Standby (Power-Down) Mode
A, S Versions
Unit
Conditions/Comments
5 to 10
5
10.5
4
4.5
1.5
V nom
V nom
V max
mA max
mA max
mA max
dB typ
dB typ
mW max
mW max
mW max
AV
DD
= DV
DD
= +5 V, V
SS
= 0 V; Typically 25 mW
AV
DD
= DV
DD
= +5 V, V
SS
= –5 V; Typically 30 mW
AV
DD
= DV
DD
= +5 V, V
SS
= 0 V or –5 V; Typically 7 mW
±
5% for Specified Performance
±
5% for Specified Performance
For Specified Performance
V
SS
= –5 V
Rejection w.r.t. AGND; Assumes V
BIAS
Is Fixed
90
45
52.5
15
NOTES
16
The AD7711A is specified with a 10 MHz clock for AV
DD
voltages of 5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V. Operating with AV
DD
voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0 C to 70 C temperature range.
17
The
±
5% tolerance on the DV
DD
input is allowed provided that DV
DD
does not exceed AV
DD
by more than 0.3 V.
18
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed
120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz.
19
PSRR depends on gain: Gain of 1: 70 dB typ; Gain of 2: 75 dB typ; Gain of 4: 80 dB typ; Gains of 8 to 128: 85 dB typ. These numbers can be improved (to 95 dB
typ) by deriving the V
BIAS
voltage (via Zener diode or reference) from the AV
DD
supply.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25∞C, unless otherwise noted.)
ORDERING GUIDE
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Model
AD7711AAR
AD7711ASQ
Temperature Range
–40∞C to +85∞C
–55∞C to +125∞C
Package Options*
RW-24
Q-24
*R
= SOIC, Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7711A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D
AD7711A
TIMING CHARACTERISTICS
Parameter
f
CLK IN4, 5
400
10
8
0.4
¥
t
CLK IN
0.4
¥
t
CLK IN
50
50
1000
0
0
2
¥
t
CLK IN
0
4
¥
t
CLK IN
+ 20
4
¥
t
CLK IN
+ 20
t
CLK IN
/2
t
CLK IN
/2 + 30
t
CLK IN
/2
3
¥
t
CLK IN
/2
50
0
4
¥
t
CLK IN
+ 20
4
¥
t
CLK IN
0
10
kHz min
MHz max
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
1, 2
(DV
DD
= +5 V
5%; AV
DD
= +5 V or +10 V
3
, 5%; V
SS
= 0 V or –5 V 10%; AGND = DGND
= 0 V; f
CLKIN
= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
(A, S Versions)
Unit
Conditions/Comments
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
AV
DD
= 5 V
±
5%
AV
DD
= 5.25 V to 10.5 V
Master Clock Input Low Time. t
CLK IN
= 1/f
CLK IN
Master Clock Input High Time
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
SYNC
Pulse Width
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
RFS
Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
TFS
to SCLK Falling Edge Delay Time
TFS
to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
2
t
CLK IN LO
t
CLK IN HI
t
r6
t
f 6
t
1
Self-Clocking Mode
t
2
t
3
t
4
t
5
t
6
t
7 7
t
8 7
t
9
t
10
t
14
t
15
t
16
t
17
t
18
t
19
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
The AD7711A is specified with a 10 MHz clock for AV
DD
voltages of 5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5
The AD7711A is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
京公网安备 11010802033920号
EEWORLD
