W78IRD2 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION .......................................................................................................... 3
FEATURES.................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................. 4
PIN DESCRIPTION ..................................................................................................................... 5
FUNCTIONAL DESCRIPTION .................................................................................................... 6
5.1
5.2
5.3
5.4
5.5
5.6
6.
7.
8.
RAM ................................................................................................................................ 6
Timers/Counters .............................................................................................................. 6
Clock ............................................................................................................................... 7
Power Management ........................................................................................................ 7
Reduce EMI Emission ..................................................................................................... 7
Reset ............................................................................................................................... 7
SPECIAL FUNCTION REGISTER .............................................................................................. 8
PORT 4 AND BASE ADDRESS REGISTERS .......................................................................... 30
INTERRUPTS ............................................................................................................................ 32
8.1
8.2
External Interrupts 2 and 3 ............................................................................................ 32
Interrupt Priority ............................................................................................................. 32
Timer 0 and Timer 1 ...................................................................................................... 33
Timer/Counter 2 ............................................................................................................ 35
MODE 0 ......................................................................................................................... 38
MODE 1 ......................................................................................................................... 39
MODE 2 ......................................................................................................................... 40
MODE 3 ......................................................................................................................... 41
Framing Error Detection ................................................................................................ 42
Multi-Processor Communications ................................................................................. 42
PCA Capture Mode ....................................................................................................... 47
16-bit Software Timer Comparator Mode ...................................................................... 48
High Speed Output Mode .............................................................................................. 48
Pulse Width Modulator Mode ........................................................................................ 49
Watchdog Timer ............................................................................................................ 50
9.
PROGRAMMABLE TIMERS/COUNTERS ................................................................................ 33
9.1
9.2
10.
ENHANCED FULL DUPLEX SERIAL PORT ............................................................................ 38
10.1
10.2
10.3
10.4
10.5
10.6
11.
PROGRAMMABLE COUNTER ARRAY (PCA) ......................................................................... 44
11.1
11.2
11.3
11.4
11.5
12.
13.
14.
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT) ................... 51
DUAL DPTR .............................................................................................................................. 51
TIMED-ACCESS PROTECTION ............................................................................................... 52
Publication Release Date: October 2, 2006
-1-
Revision A7
W78IRD2
15.
16.
17.
18.
IN-SYSTEM PROGRAMMING (ISP) MODE ............................................................................. 54
H/W REBOOT MODE (BOOT FROM LDROM) ........................................................................ 58
OPTION BITS REGISTER ........................................................................................................ 59
ELECTRICAL CHARACTERISTICS ......................................................................................... 60
18.1
18.2
18.3
Absolute Maximum Ratings .......................................................................................... 60
D.C. Characteristics ...................................................................................................... 60
A.C. Characteristics....................................................................................................... 62
19.
20.
TIMING WAVEFORMS ............................................................................................................. 64
TYPICAL APPLICATION CIRCUITS ......................................................................................... 66
20.1
20.2
External Program Memory and Crystal ......................................................................... 66
Expanded External Data Memory and Oscillator .......................................................... 67
21.
22.
PACKAGE DIMENSIONS.......................................................................................................... 68
APPLICATION NOTE ................................................................................................................ 70
22.1
22.2
In-System Programming (ISP) Software Examples ...................................................... 70
How to Use Programmable Counter Array .................................................................... 74
23.
REVISION HISTORY................................................................................................................. 75
-2-
W78IRD2
1. GENERAL DESCRIPTION
The W78IRD2 is an 8-bit microcontroller which is pin- and instruction-set-compatible with the standard
80C52. The W78IRD2 contains a 64-KB Flash EPROM whose contents may be updated in-system by
a loader program stored in an auxiliary, 4-KB Flash EPROM. Once the contents are confirmed, it can
be protected for security.
The W78IRD2 also contains 256 bytes of on-chip RAM; 1 KB of auxiliary RAM; four 8-bit, bi-directional
and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; and a serial port.
These peripherals are all supported by nine interrupt sources with 4 levels of priority.
The W78IRD2 has two power-reduction modes: idle mode and power-down mode, both of which are
software-selectable. Idle mode turns off the processor clock but allows peripherals to continue
operating, while power-down mode stops the crystal oscillator for minimum power consumption.
Power-down mode can be activated at any time and in any state without affecting the processor.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS microcontroller
Pin-compatible with standard 80C52
Instruction-set compatible with 80C52
Four 8-bit I/O ports; Port 0 has internal pull-up resisters enabled by software
One extra 4-bit I/O port with interrupt and chip-select functions
Three 16-bit timers
Programmable clock out
Programmable Counter Array (PCA) with PWM, Capture, Compare and Watchdog functions
9 interrupt sources with 4 levels of priority
Full-duplex serial port with framing-error detection and automatic address recognition
64-KB, in-system-programmable, Flash EPROM (AP Flash EPRAOM)
4-KB auxiliary Flash EPROM for loader program (LD Flash EPROM)
256-byte on-chip RAM
1-KB auxiliary RAM, software-selectable
Software Reset
12 clocks per machine cycle operation (default). Speed up to 20 MHz.
6 clocks per machine cycle operation set by the writer. Speed up to 12 MHz.
2 DPTR registers
Low EMI (inhibit ALE)
Built-in power management with idle mode and power down mode
Code protection
Packages:
—
Lead Free (RoHS) DIP 40: W78IRD2A25DL
—
Lead Free (RoHS) PLCC 44: W78IRD2A25PL
-3-
Publication Release Date: October 2, 2006
Revision A7
W78IRD2
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
T
2
,
P
1
.
0
/
I
N
T
3
,
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P
T S 4
A S .
L
0
1
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4,
P0.5,
P0.6,
P0.7,
EA
P4.1
ALE
AD4
AD5
AD6
AD7
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-4-
W78IRD2
4. PIN DESCRIPTION
SYMBOL
TYPE*
DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute
instructions in external ROM. The ROM address and data are not presented on
the bus if the
EA
pin is high.
PROGRAM STORE ENABLE:
PSEN
indicates external ROM data is on the
Port 0 address/data bus. If internal ROM is accessed, no
PSEN
strobe signal
is present on this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: If this pin is set high for two machine cycles while the oscillator is
running, the W78IRD2 is reset.
CRYSTAL 1: Crystal oscillator input or external clock input.
CRYSTAL 2: Crystal oscillator output.
GROUND: ground potential.
POWER SUPPLY: Supply voltage for operation.
PORT 0: 8-bit, bi-directional I/O port, the same as that of the standard 80C52
Port 0 has internal pull-up resisters enabled by software.
PSEN
O H
ALE
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0
−
P0.7
P1.0
−
P1.7
P2.0
−
P2.7
P3.0
−
P3.7
P4.0
−
P4.3
O H
I L
I
O
I
I
I/O D
I/O H PORT 1: 8-bit, bi-directional I/O port, the same as that of the standard 80C52.
I/O H
PORT 2: 8-bit, bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits when accessing external memory.
I/O H PORT 3: 8-bit, bi-directional I/O port, the same as that of the standard 80C52.
I/O H PORT 4: 4-bit, bi-directional I/O port with chip-select functions.
* Note: TYPE
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
-5-
Publication Release Date: October 2, 2006
Revision A7
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