Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
16K/64K/512 FLASH
89C536/89C538
DESCRIPTION
The 89C536/89C538 are Single-Chip 8-Bit Microcontrollers
manufactured in advanced CMOS process and are derivatives of
the 80C51 microcontroller family. All the devices have the same
instruction set as the 80C51.
The devices also have four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, two-priority-level, nested interrupt
structure, UART and on-chip oscillator and timing circuits. For
systems that require extra data memory capability up to 64k bytes,
each can be expanded using standard TTL-compatible memories
and logic.
The 89C536/89C538 contain a non-volatile FLASH program
memory (16k bytes in the 89C536, and 64k bytes in the 89C538).
The devices have 512 bytes of RAM data memory.
FEATURES
•
80C51 Central Processing Unit
•
16k
×
8 (89C536) or 64k
×
8 (89C538), FLASH EPROM Program
Memory
•
512
×
8 RAM, externally expandable to 64k
×
8 Data Memory
•
Three 16-bit counter/timers
•
Up to 3 external interrupt request inputs
•
6 interrupt sources with 2 priority levels
•
Four 8-bit I/O ports
•
Full-duplex UART
•
Power control modes
–
Idle mode
–
Power down mode, with wakeup from power down using
external interrupt
•
44-pin PLCC and QFP packages
ORDERING INFORMATION
PART NUMBER
P89C536NBA A
P89C536NBB B
P89C538NBA A
P89C538NBB B
MEMORY SIZE
16k bytes
16k bytes
64k bytes
64k bytes
TEMPERATURE RANGE (°C) AND PACKAGE
0 to +70, 44-pin Plastic Leaded Chip Carrier
0 to +70, 44-pin Plastic Quad Flat Package
0 to +70, 44-pin Plastic Leaded Chip Carrier
0 to +70, 44-pin Plastic Quad Flat Package
FREQ.
(MHz)
33
33
33
33
DRAWING
NUMBER
SOT187-2
SOT307-2
SOT187-2
SOT307-2
1998 Apr 24
2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
16K/64K/512 FLASH
89C536/89C538
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
CC
P0.0–0.7
LCC
1, 22
23, 44
43–36
QFP
16, 39
17, 38
37–30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and
received code bytes during EEPROM programming. External pull-ups are required during program
verification.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 1 also receives the low-order address byte during program memory
verification.
Alternate functions for Port 1 include:
2
3
P2.0–P2.7
24–31
40
41
18–25
I/O
I
I/O
T2 (P1.0):
Timer/Counter 2 external count input
T2EX (P1.1):
Timer/Counter 2 Reload/Capture
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Some Port 2 pins
receive the high order address bits during EEPROM programming and verification.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 3 also serves the special features of the 80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal diffused resistor to V
SS
permits a power-on reset using only an external capacitor to V
CC
.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EEPROM programming.
Program Store Enable:
The read strobe to external program memory. When the processor is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN is
not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low to enable
the device to fetch code from external program memory. If EA is held high, the device executes from
internal program memory. This pin also receives the 12V programming supply voltage (V
PP
) during
EPROM programming. EA is internally latched on Reset.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
P1.0–P1.7
2–9
40–44,
1–3
I/O
P3.0–P3.7
11,
13–19
5,
7–13
I/O
11
13
14
15
16
17
18
19
RST
ALE/PROG
10
33
5
7
8
9
10
11
12
13
4
27
I
O
I
I
I
I
O
O
I
O
PSEN
32
26
O
EA/V
PP
35
29
I
XTAL1
XTAL2
21
20
15
14
I
O
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
CC
+ 0.5V or V
SS
– 0.5V, respectively.
1998 Apr 24
5
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