*ON/OFF input must be actively terminated. Tie to V
IN
if this function is not to be used.
**Minimum capacitance is shown to ensure stability (may be increased without limit). Ceramic capacitor required for output (see Application Hints).
***Reduces output noise (may be omitted if application is not noise critical). Use ceramic or film type with very low leakage current (see Application Hints).
Connection Diagrams
5-Lead Small Outline Package (M5)
micro SMD, 5 Bump Package (BPA05 & BLA05)
10129503
Top View
See NS Package Number MF05A
For ordering information see
Table 1
10129523
Note:
The actual physical placement of the package marking will vary from
part to part. Package marking contains date code and lot traceability
information, and will vary considerably. Package marking does not correlate
to device type.
Top View
See NS Package Number BPA05 & BLA05
Pin Descrption
Name
SOT-23
V
IN
GND
ON/OFF
BYPASS
V
OUT
1
2
3
4
5
Pin Number
micro SMD
C3
A1
A3
B2
C1
Input Voltage
Common Ground (device substrate)
Logic high enable input
Bypass capacitor for low noise operation
Regulated output voltage
Function
www.national.com
2
LP2985LV
Ordering Information
TABLE 1. Package Marking and Ordering Information
Output Voltage (V)
Grade
Order Information
Package
Marking
LF7A
LF7A
LF7B
LF7B
LCHA
LCHA
LCHB
LCHB
LAYA
LAYA
LAYB
LAYB
LCDA
LCDA
LCDB
LCDB
Supplied as:
5-Lead Small Outline Package (M5)
1.35
1.35
1.35
1.35
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
A
A
STD
STD
LP2985AIM5X-135
LP2985AIM5-135
LP2985IM5X-135
LP2985IM5-135
LP2985AIM5X-1.5
LP2985AIM5-1.5
LP2985IM5X-1.5
LP2985IM5-1.5
LP2985AIM5X-1.8
LP2985AIM5-1.8
LP2985IM5X-1.8
LP2985IM5-1.8
LP2985AIM5X-2.0
LP2985AIM5-2.0
LP2985IM5X-2.0
LP2985IM5-2.0
LP2985AIBP-1.5
LP2985AIBPX-1.5
LP2985IBP-1.5
LP2985IBPX-1.5
LP2985AIBP-1.8
LP2985AIBPX-1.8
LP2985IBP-1.8
LP2985IBPX-1.8
LP2985AIBL-1.8
LP2985AIBLX-1.8
LP2985IBL-1.8
LP2985IBLX-1.8
LP2985AITP-1.5
LP2985AITPX-1.5
LP2985ITP-1.5
LP2985ITPX-1.5
LP2985AITP-1.8
LP2985AITPX-1.8
LP2985ITP-1.8
LP2985ITPX-1.8
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
3000 Units on Tape and Reel
1000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
250 Units on Tape and Reel
3000 Units on Tape and Reel
micro SMD, 5 Bump Package (BPA05 - 170 µm ball)
micro SMD, 5 Bump Package (BLA05 - 300 µm ball)
micro SMD, 5 Bump Package (TPA05 - 170 µm ball)
3
www.national.com
LP2985LV
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Operating Junction Temperature
Range
Lead Temp. (Soldering, 5 sec.)
ESD Rating (Note 2)
Power Dissipation (Note 3)
−65˚C to +150˚C
−40˚C to +125˚C
260˚C
2 kV
Internally Limited
Input Supply Voltage (Survival)
Input Supply Voltage (Operating)
Shutdown Input Voltage (Survival)
Output Voltage (Survival, (Note 4))
I
OUT
(Survival)
Input-Output Voltage (Survival,
(Note 5))
−0.3V to +16V
2.2V to +16V
−0.3V to +16V
−0.3V to +9V
Short Circuit
Protected
−0.3V to +16V
Electrical Characteristics
(Note 10)
Limits in standard typeface are for T
J
= 25˚C. and limits in
boldface type
apply over the full operating temperature range. Un-
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FPGA/CPLD
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