-..
ANALOG
W
DEVICES
PRELIMINARY TECHNICAL DATA
FEATURES
DAS1150
Resistor-Programmable Gain (1
=
1000V!V)
High Accuracy with Low Level Input Signals
Low Cost
High Throughput Rate and High Gain
DAS1151
Software-Programmable Gain (1, 2, 4, 8V!V)
Provides Gain for Signal Conditioning and High
Throughput Rate
Gain Ratio Error: :1:0.02% max
FS
LowLevelInput,12-Bit
DataAcquisition odules
M
OBS
GENERAL DESCRIPTION
The DAS1150 and DAS1151 are two data acquisition modules
designed, built and tested to meet system data acquisition re-
quirements. Each device comprises an instrumentation ampli-
fier, sample-hold amplifier and 12-bit successive approximation
AID
converter. These products are used on Analog Devices
Real Time Interface boards as data acquisition systems to
interface with microcomputer boards.
With the DAS1150 and DAS1151, users can apply gain to the
instrumentation amplifier for signal conditioning and still
achieve high speed data conversion. The difference between
models is how the gain is controlled. With the DAS 1150, the
designer sets the gain from 1 to 1000 V/V with a resistor, RG.
The DAS1151 has gains of 1-2-4-8 that are software-program-
mable.
OLE
TE
ADDRESS
Ao
to :l:10V with the DAS1150 or any of 4 input voltage ranges
with the DAS1151. The instrumentation amplifier drives a
sample-hold amplifier, whose function is to hold the selected
analog input signal at a constant level while the AID converter
is making a conversion.
The AID converter is a high speed 12-bit successive approxi-
mation device that has been designed using Analog Devices
AD562 IC DI A converter with a precision reference source, a
high speed comparator and successive approximation logic.
DESIGN FEATURES AND USER BENEFITS
The DAS1150 and DAS1151 offer true high-speed 12-bit per-
formancewith maximum overall error at unity gain of :1:1least
significant bit (LSB). This performance is guaranteed at a
25kHz throughput rate. There is very little performance lost at'
high gains. For example, at gain of 1000, the DAS1l50 has a
throughput of 13kHz and an overall accuracy of :l:2LSB. The
DAS1151 with its software-programmable gain provides dy-
namic range expansion as well as the flexibility of using differ-
ent gain settings to accommodate different input signal levels.
The resistor-programmable-gain DAS 1150 may be used for in-
put ranges from 1OmV full scale to :l:10V full scale with very.
little loss of speed and no degradation of linearity at high gain.
THEORY OF OPERATION
Block diagrams of the DAS 1150 and DAS 1151 are shown in
Figures 1 and 2. Analog input signals are applied to the input
of the instrumentation amplifier. The instrumentation ampli-
.
fier
ADDRESSA,
CONTROl
IN
'SV 0
DIGITAl 0
GROUND
+
R"'RENCE
OUT
O>FSET
ADJ
SUMMING
POINT
R"'RENCE
BIPOlAR
'OV"'AN
'"V
SPAN
IN
Df'SET
Figure
1.
DAS1151
Block Diagramand Pin Designations
is gain-programmable by the user via a resistor (DAS1150)
or TTL/CMOS logic (DAS1151). This featUre permits the user
to operate the module on any input voltage range from :l:10mV
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
Route 1 Industrial Park; P.O. Box 280; Norwood, Mass.02062
Tel: 617/329-4700
TWX: 710/394-6577
West Coast
Mid-West
Texas
714/842-1717
312/894-3300
214/231.5094
SPECIFICATIONS
@+25°Cand ratedsuppliesunlessothervyisenoted)
(typical
MODELS
RESOLUTION
CHARACTERISTICS
ADC Conversion Time
IA Settling Time,
to
to
to
Throughput
20V Input Step
O.OI%@G
=
1
0.01 % @ G
=
10
0.05% @ G = 1000
DAS1l50
12
25/1s max
15/1s max
15/1s
50/1s
25kHz
25kHz
13.3 kHz
3Ms
90ns
20ns
5ns
2mV/s
:tlLSB max
:t2LSB max
:tl/2LSB (:tlLSB max)
to Zero
to Zero
/1V/DC
Reading/C
4.02
1102.11
MAX
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
(G
=
1-8) 1OMsmax
N.A.
N.A.
(G
1---2.02151.31 -I
MAX
~
UT
I
Rate G = 1
G = 10
G = 1000
=
1-8)
28.5kHz
LU
-':::-;;:,2513.21
MIN
I
04~1~.71
N.A.
N.A.
Sample-Hold
Acquisition Time
Aperture Delay Time
Aperture Time
Aperture Uncertainty Time
Droop Rate
Overall Errorl @ G
@G
Nonlinearity Error
Offset Error
Gain Error
OBS
=
1
=
1000
TEMPERATURE
Offset (RTI)
Gain (RTI)
Differential
COEFFICIENTS
ANALOG INPUTS
Voltage Input Range
ADC Input Ranges
( ADC FS
\" GAIN
(G
=
8)
:t2LSB max
)
10mV to :tl0V
0 to +5V
0 to +10V
:t2.5V
:t5V
:tl0V
Instrumentation
Gain
Amplifier
Resistor-Programmable
.
11~00(20H2
RG
N.A.
--
1O8n
20nA
2nA
Gain Range
Gain Equation
Gain Ratio Error2
Input Impedance
Bias Current
Offset Current
Offset
(RTI)
DIGIT AL INPUTS
ADC Convert Command
SHA Mode Control
PGA Gain Control
DIGITAL OUTPUT
Parallel Data Output
Unipolar
Bipolar
Serial Data Output
Unipolar
Bipolar
Status Output
~
~
\
)
OLE
TE
:t30/1V/C
*
0.625V to :tl0Y
BOTTOMVIEW
--1
1--0.,
12.541GRID
NOTES,
TERMINAL PINS INSTALLED ONLY IN SHADED
HOLE LOCATIONS.
SEE TABLE BELOW FOR PIN DELETIONS.
MODULE WEIGHT, 3.5 OUNCES 199.3 GRAMSI.
ALL PINS ARE GOLD PLATED HALF.HARD
BRASS IMIL.G..5204!.
0.019'" ".0°""
10.40
'0.03mml
DIA.
So f tw are-Pro gramm a bIe
1,2,4,8
See Table 4
:to.02% FS max
2nA
500pA
MATING SOCKET: AC1577
(4 per, $3 each)
:t50MV
Positive Pulse, TTL Compatible,
min Width
lOOns
Positive Pulse TTL Compatible Logic
"1" = Hold, Logic "0" = Sample
N.A.
TTL Compatible,
6TTL Loads/Bit
Positive True Binary
Positive True Offset Binary
or Two's Complement
6 TTL Loads
Positive True Binary NRZ Format,
MSB First
Positive True Offset Binaty, NRZ Format,
MSB First
Logic "1" During Conversion, TTL
Compatible, 4TTL Loads, Complement
also Available
480kHz, TTL Compatible,
6TTL Loads
+5V dc :t5% @ 130mA (170mA max)
:t15V dc :t3% @ 30mA (40mA max)
:t15V dc :t3% @ 30mA (40mA max)
0 to +70DC
-55DC to +85DC
$199
$249
Clock
POWER REQUIREMENTS
TEMPERATURERANGE
Operating
Storage
PRICE
(1-24)
NOTES
I
Overall error is specified with gains and
offset trimmed and is defined as the
deviation from a straight line passing
through the end points of the range.
2Once the full scale has been calibrated
on any gain setting, switching to any
other gain setting will cause no more
than a 0.02% shift in full scale.
*Specifications same as DAS1150.
Specifications subject to change with-
out notice.
-~~--
+IN
+15V
-15V
RG
SHA
OUT
4
4
36 +15V
34 -15V
,,'
+IN 39
-IN 37:t:
ANALOG
IN
4
-IN
10pF
SOLID
TANTALUM
{
RG 43.
RG41.1-"
-}.'
+15V 0.1
ANALOG
COMMON
-,5VO
{
:J .-
.l
~.
r
r
.
CLOCK
CONVERT
COMMAND
STATUS
STATUS
SERIALOUT
MSB
MSB
BIT 2
BIT 3
BIH
BITS
BIT.
BIT 7
BIT a
BITS
r------,
22 ANAGND
20 SHAOUT
A, 51'-
A, 50.1"" i.N2"?:
GTl,
SHACONTROL
53
I
+5VO
g~~'J~6 0
~
.,8
15
TURN
GAIN
ADJUSTMENT
SUM
REF OUT
ZERO
REF IN
BIIN
+5V
CONV COM
STATUS
STATUS
56
57
58
59.
loon
OBS
OFFSET ADJ
SUMMING
POINT
REFERENCE
OUT
17
16
15
14
BIT 'A
BIT 11
LSB
.,3 10V
12 20V
11 ANAGNO
OGL
:
3
Figure
2.
DAS1150
Block
Diagram and Pin Designations
GROUNDING PRACTICE
Attention should be given to the methods of connection for
electrical returns and voltage reference points. Analog ground
and digital ground are provided. These data acquisition systems
do not have an internal connection between analog ground and
digital ground and, thus, a connection must be provided in the
external circuitry. The choice of an optimum "star" point for
these grounds is an important consideration in the performance
of the system. No strict rules can be given, only the general
guidelines that the grounding should be arranged in such a
manner as to avoid ground loops and to minimize the coupling
of voltage drops between the high current carrying logic sup-
ply ground and the sensitive analog circuit sections.
1. If the :!:15V power supply is floating (for optimum analog
accuracy), connect its common to analog ground. If the
:!:15V power supply is not floating, connect its common to
digital ground.
2. Connect the +5V supply common to digital ground. If this
supply also powers additional equipment, run separate,
parallel returns to the equipment ground and to digital
ground.
OLE
TE
BIPOLAR OFFSET
10V SPAN
20V SPAN
REFERENCE IN
.7
.6
.5
.4
.3
.2
MSB
MSB
BIT2
BIT3
BIT4
.,
BIT5
BIT6
SERIAL 66.
LSB 67.
BIT 11 68.
BIT 10 69.
BIT 9 70.
BIT 8 71.
BIT 7 72.
BOTTOM VIEW
NOTES,
'THESE PINS APPEAR ON
DAS1150
ONLY.
'THESE PINS APPEAR ON
DAS1151 ONLY.
'ANALOG
AND DIGITAL GROUNDS SHOULD BE
TIED TOGETHER AT ONE POINT AS CLOSETO
THE MODULE AS POSSIBLE.
'SHOULD BE LOCATED WITHIN 1" FROM MODULE.
Figure
3.
Module Connections for:!: 10V Range
Figure 3 shows the connections required to operate the
DAS1150 or DAS1151 with a :!:10V input range. Table 1
shows connections for ADC input ranges.
Input Range
0 to +5V
:!:2.5V
0 to +10V
:!:5V
:!:10V
Pin
Pin
Pin
Pin
Pin
17
17
17
17
17
Jumper
to 15, Pin
to 14, Pin
to 15, Pin
to 14, Pin
to 14, Pin
20
20
20
20
20
to
to
to
to
to
18
18
13
13
12
Table
1.
ADC Input Range Connections
70
60
50
3. Single-ended input signals should only be returned to anaiog
ground. If this is not possible, then connect the input sig-
nals in the differential configuration.
4. Connect computer ground to digital ground. Use heavy wire
or ground planes.
5. The computer chassis should be connected to the computer
and power supply grounds at only one point.
6. Connect the third wire ground from main ac power input
to the computer power supply return.
7. Bias return path should always be provided.
.
"-
I
40
~
;:: 30
20
10
ol
1
GAIN
Figure4. Typical Settling Time Curvesfor DAS1150
GAIN AND OFFSET ADJUSTMENT PROCEDURE
ADC
ANALOG
INPUT
I
DIGITAL
OUTPUT
+5V RANGE
+4.9988V
+2.5000V
+0.6250V
+0.0012V
+O.OOOOV
.~.,~""--"
.
+1OVR.ANGET-BINARYCOOE-
+9.99'~~1ITT1i1T1fiT~-"
+5.0000V
I 100000000000
+1.2500V
001000000000
+0.0024V
000000000001
+O.OOOOV
000000000000
TIMING
The "0" to "1" transition of the CONVERT COMMAND in-
put resets the MSB output to Logic "0" and the CLOCK
STATUS, MSB, and BIT 2 through BIT 12 outputs to Logic
"1 ". Nothing further happens until the CONVERT COM-
MAND retUrns to Logic "0", at which time the conversion
proceeds.
With the MSB in the Logic "0" state, the internal digital-to-
analog converter's
(DI
A) output is compared with the analog
.input (SHA OUT). If the
D/A
output is less than the analog in-
put, the first "0" to "1" clock transition resets the MSB Logic
"1 ". If the D/ A output is greater than the analog input, the
MSB remains at Logic "0".
The first "0" to "1" clock transition also sets the BIT 2 out-
put to Logic "0" and another comparison is made. This pro-
cess continues through each successive bit until the BIT 12
(LSB) comparison is completed. At this time the STATUS out-
put returns to Logic "0" and the conversion cycle ends.
The SERIAL DATA output is of the non-retUrn-to-zero (NRZ)
type. The data is available, MSB first, 40ns after each of the
twelve "0" to "1" clock transitions.
~g~~~~';,
Table
2.
Nominal Unipolar Input-Output
ADC
~~~~!OG
,I.~~UT
-~
:!:5V
tl0V
+9.9951V
+5.0000V
+0.0049V
+O.OOOOV
-10.0000V
L"-~~~I2lliill\!;.Q
Relationships
UTPUr
r--
CD
m
I
m
I
m
~
OBS
Table
3.
Nominal Bipolar Input-Output
:!:2.5V
RANGE .~~~._-~-~
+4.9976V
+2.4988V
+2.5000V
+1.2500V
+0.0024V
+0.0012V
+O.OOOOV
+O.OOOOV
-5.0000V
-2.5000V
OFFSET BINAR
..~- CODE,....
111111111111
110000000000
100000000001
100000000000
000000000000
O'S
EMENT
CODE
01 fiTillli 1111
0100000000000
0000000000001
0000000000000
1000000000000
10
()
Relationships
OFFSET CALIBRATION
For unipolar mode set the input voltage precisely to the value
of 1LSB (see Table 2) and adjust the offset potentiometer
until the converter is just on the verge of switching from
000000000000 to 000000000001.
For bipolar mode set the input voltage precisely to zero volts.
Adjust the offset potentiometer until the offset binary coded
units are just on the verge of switching from 011111111111 to
100000000000 and two's complement coded units are just on
the verge of switching 111111111111 to 000000000000.
GAIN CALIBRATION
The analog input values given in Tables 2 and 3 are values that
should be present at the input to the internal ADC. The value
of the analog input will be affected by the gain of the
OLE
TE
JL
J
CLOCK
STATUS
L-
MSB~
BIT2
~
BIT 3
u
BIT 11
-
LSB
~
r--L
BIn
BIT 11
OUTPUT
SERIAL
~""""
MSB
BIT 3
s-
LSB
PREVIOUS WORO,
NEW WORD,
111...11
101...01
ADC FULL SCALE
A
NALO G IN
d I
mo u e, I.e.,
"GAIN
Set the ADC input voltage precisely to plus full scale minus
1 1/2 LSB's: +4.9982V for 5V units, +9.9963V for :tlOV
units, +2.4982V for :t2.5V units, +4.9963V for :t5V units, or
+9.9926V for :tlOV units. Adjust the lOOn variable gain re-
sistor until binary and offset binary coded units are just on
the verge of switching from 11111111111 0 to 111111111111
and two's complement coded units are just on the verge of
switching from 011111111110 to 011111111111.
INCREASING THROUGHPUT RATE
Throughput rates for the DAS1150 and DAS1151 can be
increased by the use of the OVERLAP MODE, i.e. updating
the input while the ADC is making a conversion. Typical
throughput rates can be increased to 35kHz @ G
= 1,
20kHz @ G = 1000 for the DAS1150
and 35kHz for G
.
j
)
Figure
5.
ADC Timing Diagram
AMPLIFIER GAIN
The DAS1150 instrumentation amplifier gain may be set to any
any value between 1 and 1000 by connecting an external gain
resistor between pins 41 and 43. The resistance is determined
by the formula G
=
1 + (2~k~ ). RG should be located as
close as possible to the module pins. It must be noted that the
TC of RG directly affects the gain temperature coefficient of
the DAS1150. A high quality metal film resistor 0.1 % is
recommended.
The gain of the DAS1151 is programmed by loading the
proper code into the gain address, as shown in Table 4.
ADDRESS INPUTS DAS1151
GAIN
Al
Ao
0
0
1
0
1
2
1
0
4
1
1
8
q
::::>
~
z
0
w
=
1
thm 8 for the DAS 1151. When the IA settling time is less
than or equal to the sum of SHA acquisition time and ADC
conversion time,
28Jls,
the DAS throughput rate equals
1/28Jls
or 35kHz. When IA settling time is greater than
28Jls
(see Figure 4), the DAS throughput rate equals the
reciprocal of IA settling time.
I-
Z
ex:
a..
Table
4.
DAS1151 Gain State Truth
Table
---
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