a
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 521/1036
Less than 0.1% Error Over a Dynamic Range of 500 to 1
The AD7751 Supplies
Average Real Power
On the
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for Calibra-
tion and Supplies
Instantaneous Real Power
Data
Continuous Monitoring of the Phase and Neutral Current
Allows Fault Detection in Two-Wire Distribution Systems
The AD7751 Uses the Larger of the Two Currents (Phase
or Neutral) to Bill—Even During a Fault Condition
Two Logic Outputs (FAULT and REVP) Can Be Used to
Indicate a Potential Miswiring or Fault Condition
Direct Drive for Electromechanical Counters and
Two-Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of
Shunt
and
Burden
Resistance
Proprietary ADCs and DSP Provide High Accuracy Over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V 8% (30 ppm/ C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
GENERAL DESCRIPTION
Energy Metering IC
with On-Chip Fault Detection
AD7751*
FUNCTIONAL BLOCK DIAGRAM
G0 G1
AV
DD
AGND
FAULT
AC/DC
DV
DD
DGND
AD7751
POWER
SUPPLY MONITOR
V1A
V1N
V1B
1,
V2P
V2N
1,
PGA
2, 8,
ADC
16
ADC
PGA
2, 8,
16
ADC
A<>B
A>B
...
110101
...
SIGNAL
PROCESSING
BLOCK
HPF
...
110101
...
B>A
PHASE
CORRECTION
MULTIPLIER
...
11011001
...
LPF
4k
2.5V
REFERENCE
CLKOUT
REF
IN/OUT
CLKIN
DIGITAL-TO-FREQUENCY
CONVERTER
SCF S0 S1 REVP CF F1 F2
RESET
The AD7751 is a high accuracy fault tolerant electrical energy
measurement IC intended for use with two-wire distribution
systems. The part specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard.
The only analog circuitry used on the AD7751 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The AD7751 incorporates a novel fault detection scheme that
both warns of fault conditions and allows the AD7751 to con-
tinue accurate billing during a fault event. The AD7751 does
this by continuously monitoring both the phase and neutral
(return) currents. A fault is indicated when these currents
differ by more than 12.5%. Billing is continued using the larger
of the two currents when the difference is greater than 14%.
The AD7751 supplies average real power information on the
low frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real
power information. This output is intended to be used for cali-
bration purposes.
The AD7751 includes a power supply monitoring circuit on the
AV
DD
supply pin. The AD7751 will remain in a reset condition
until the supply voltage on AV
DD
reaches 4 V. If the supply falls
below 4 V, the AD7751 will also be reset and no pulses will be
issues on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are matched whether the HPF in Channel 1
is on or off. An internal no-load threshold ensures that the
AD7751 does not exhibit any creep when there is no load.
The AD7751 is available in 24-lead DIP and SSOP packages.
*Protected
by U.S. Patent Nos. 5,745,323; 5,760,617; 5,862,069 and
5,872,469.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD7751–SPECIFICATIONS
Parameter
ACCURACY
1
Measurement Error
1
on Channel 1
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Phase Error
1
Between Channels
V1 Phase Lead 37°
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
(PF = 0.5 Inductive)
AC Power Supply Rejection
1
Output Frequency Variation (CF)
DC Power Supply Rejection
1
Output Frequency Variation (CF)
FAULT DETECTION
1, 2
Fault Detection Threshold
Inactive i/p <> Active i/p
Input Swap Threshold
Inactive i/p > Active i/p
Accuracy Fault Mode Operation
V1A Active, V1B = AGND
V1B Active, V1A = AGND
Fault Detection Delay
Swap Delay
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (DC)
Bandwidth
ADC Offset Error
1
Gain Error
1
Gain Error Match
1
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
CLKIN
Input Clock Frequency
LOGIC INPUTS
3
SCF, S0, S1, AC/DC,
RESET,
G0 and G1
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
A Version
0.1
0.1
0.1
0.1
±
0.1
±
0.1
0.01
1
(AV
DD
to=TDV
DD
= 5 V C to5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
T
= –40
+85 C)
MIN
MAX
B Version
Unit
Test Conditions/Comments
Channel 2 with Full-Scale Signal (± 660 mV), 25°C
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Line Frequency = 45 Hz to 65 Hz
AC/DC = 0 and AC/DC = 1
AC/DC = 0 and AC/DC = 1
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz
Ripple on AV
DD
of 200 mV rms @ 100 Hz
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms,
AV
DD
= AV
DD
= 5 V
±
250 mV
See Fault Detection Section, PF = 1
0.1
0.1
0.1
0.1
±
0.1
±
0.1
0.01
% Reading typ
% Reading typ
% Reading typ
% Reading typ
Degrees(°) max
Degrees(°) max
% Reading typ
0.01
0.01
% Reading typ
12.5
14
0.1
0.1
3
3
±
1
400
14
±
15
±
4
±
0.2
2.7
2.3
3.7
10
±
200
30
12.5
14
0.1
0.1
3
3
±
1
400
14
±
15
±
4
±
0.2
2.7
2.3
3.7
10
±
200
30
60
4
1
% typ
% of Active typ
% Reading typ
% Reading typ
Second typ
Second typ
V max
kΩ min
kHz typ
mV max
% Ideal typ
% Ideal typ
V max
V min
kΩ min
pF max
mV max
ppm/°C typ
ppm/°C max
(V1A or V1B Active)
(V1A or V1B Active)
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
See Analog Inputs Section
V1A, V1B
,
V1N, V2N and V2P to AGND
CLKIN = 3.58 MHz
CLKIN/256, CLKIN = 3.58 MHz
See Terminology and
External 2.5 V Reference, Gain = 1,
V1 = V2 = 660 mV dc
External 2.5 V Reference
2.5 V + 8%
2.5 V – 8%
Nominal 2.5 V
Note All Specifications for CLKIN of 3.58 MHz
4
1
MHz max
MHz min
2.4
0.8
±
3
2.4
0.8
±
3
V min
V max
µA
max
DV
DD
= 5 V
±
5%
DV
DD
= 5 V
±
5%
Typically 10 nA, V
IN
= 0 V to DV
DD
Input Capacitance, C
IN
10
10
pF max
–2–
REV. 0
AD7751
Parameter
LOGIC OUTPUTS
3
F1 and F2
Output High Voltage, V
OH
4.5
Output Low Voltage, V
OL
0.5
CF, FAULT and REVP
Output High Voltage, V
OH
4
Output Low Voltage, V
OL
0.5
POWER SUPPLY
AV
DD
DV
DD
AI
DD
DI
DD
4.75
5.25
4.75
5.25
3
2.5
0.5
4.75
5.25
4.75
5.25
3
2.5
V max
V min
V max
V min
V max
mA max
mA max
4
V min
0.5
V max
4.5
V min
A Version B Version
Unit
Test Conditions/Comments
I
SOURCE
= 10 mA
DV
DD
= 5 V
I
SINK
= 10 mA
DV
DD
= 5 V
I
SOURCE
= 5 mA
DV
DD
= 5 V
I
SINK
= 5 mA
DV
DD
= 5 V
For Specified Performance
5 V – 5%
5 V + 5%
5 V – 5%
5 V + 5%
Typically 2 mA
Typically 1.5 mA
NOTES
1
See Terminology section for explanation of specifications.
2
See Fault Detection section of data sheet for explanation of fault detection functionality.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter
t
1 3
t
2
t
3
t
4 3
t
5
t
6
1, 2
(AV
DD
= DV
DD
= 5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
T
MIN
to T
MAX
= –40 C to +85 C)
Unit
ms
sec
sec
ms
sec
sec
Test Conditions/Comments
F1 and F2 Pulsewidth (Logic Low)
Output Pulse Period. See Transfer Function Section
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function Section
Minimum Time Between F1 and F2 Pulse
A, B Versions
275
See Table III
1/2 t
2
90
See Table IV
CLKIN/4
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs section.
Specifications subject to change without notice.
t
1
F1
ORDERING GUIDE
.t
6
.t
2
F2
Model
AD7751AN
AD7751ARS
AD7751BRS
Package Description
Plastic DIP
Shrink Small Outline Package
Shrink Small Outline Package
Package
Option
N-24
RS-24
RS-24
.t
3
t
4
.t
5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. 0
–3–
AD7751
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND
V1A, V1B, V1N, V2P and V2N . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
24-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260°C
24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7751 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
MEASUREMENT ERROR
The error associated with the energy measurement made by the
AD7751 is defined by the following formula:
Percentage Error =
Energy Registered by the AD7751 – True Energy
True Energy
PHASE ERROR BETWEEN CHANNELS
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied
±
5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
ADC OFFSET ERROR
×
100%
The HPF (High Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within
±
0.1° over a range of 45 Hz to 65 Hz and
±
0.2°
over a range 40 Hz to 1 kHz.
POWER SUPPLY REJECTION
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see an analog input signal of 0 mV to
±
15 mV, depending on gain setting. However, when the HPF is
switched on the offset is removed from the current channel and
the power calculation is not affected by this offset.
GAIN ERROR
This quantifies the AD7751 measurement error as a percentage
of reading when the power supplies are varied.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the same
input signal levels. Any error introduced is expressed as a per-
centage of reading—see Measurement Error definition.
The gain error of the AD7751 is defined as the difference be-
tween the measured output frequency (minus the offset) and
the ideal output frequency. It is measured with a gain of 1 in
Channel 1. The difference is expressed as a percentage of the
ideal frequency. The ideal frequency is obtained from the trans-
fer function—see Transfer Function section.
GAIN ERROR MATCH
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output
frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from 1 to 2,
8 or 16.
–4–
REV. 0
AD7751
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
DV
DD
Description
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7751.
The supply voltage should be maintained at 5 V
±
5% for specified operation. This pin should be
decoupled with a 10
µF
capacitor in parallel with a ceramic 100 nF capacitor.
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current
channel). A logic one on this pin enables the HPF. The associated phase response of this filter has
been internally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be
enabled in energy metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7751.
The supply should be maintained at 5 V
±
5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin
should be decoupled to AGND with a 10
µF
capacitor in parallel with a ceramic 100 nF capacitor.
Analog inputs for Channel 1. These inputs are fully differential voltage inputs with a maximum
signal level of
±
660 mV with respect to pin V1N for specified operation. Channel 1 also has a PGA
and the gain selections are outlined in Table I. The maximum signal level at these pins is
±1
V with
respect to AGND. Both inputs have internal ESD protection circuitry and an overvoltage of
±
6 V
can also be sustained on these inputs without risk of permanent damage.
Negative input pin for differential voltage inputs V1A and V1B. The maximum signal level at this
pin is
±1
V with respect to AGND. The input has internal ESD protection circuitry and in addition,
an overvoltage of
±
6 V can be sustained without risk of permanent damage. This input should be
connected directly to one side of the SHUNT or BURDEN resistor and held at a fixed potential,
i.e., AGND. See Analog Input section.
Negative and positive inputs for Channel 2 (voltage channel). These inputs provide a fully differen-
tial input pair. The maximum differential input voltage is
±
660 mV for specified operation. The
maximum signal level at these pins is
±
1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of
±
6 V can also be sustained on these inputs without risk of
permanent damage.
Reset pin for the AD7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7751 internal registers.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V
±
8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may
also be connected at this pin. In either case, this pin should be decoupled to AGND with a 10
µF
tantalum capacitor and 100 nF ceramic capacitor.
This provides the ground reference for the analog circuitry in the AD7751, i.e., ADCs and refer-
ence. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is
the ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage trans-
ducers, etc. For good noise suppression the analog ground plane should only be connected to the digital
ground plane at one point. A star ground configuration will help to keep noisy digital return currents
away from the analog circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration
output CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Select-
ing a Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively a crystal can be connected across
CLKIN and CLKOUT to provide a clock source for the AD7751. The clock frequency for specified
operation is 3.579545 MHz. Crystal load ceramic capacitors of 33 pF should be used with the
gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN.
This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. See Fault Detection section.
The logic output will be reset to zero when a fault condition is no longer detected.
2
AC/DC
3
AV
DD
4, 5
V1A, V1B
6
V1N
7, 8
V2N, V2P
9
10
RESET
REF
IN/OUT
11
AGND
12
13, 14
SCF
S1, S0
15, 16
17
G1, G0
CLKIN
18
CLKOUT
19
FAULT
REV. 0
–5–
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