DATA SHEET
Integrated
ICS840001I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK
ICS840001I
Circuit
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
GENERATOR
Systems, Inc.
PRELIMINARY
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS840001I is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from ICS. The
ICS840001I uses a 26.5625MHz crystal to
synthesize either 106.25MHz or 212.5MHz, using
the FREQ_SEL pin. The ICS840001I has excellent phase jitter
performance, over the 637kHz – 5MHz integration range. The
ICS840001I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
F
EATURES
•
1 LVCMOS/LVTTL output, 7Ω typical output impedence
•
Crystal oscillator interface designed for 26.5625MHz,
18pF parallel resonant crystal
•
Selectable 106.25MHz or 212.5MHz output frequency
•
VCO range: 560MHz to 680MHz
•
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 5MHz): 0.70ps (typical)
•
3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
ICS
F
UNCTION
T
ABLE
Input
FREQ_SEL
0
1
Crystal: 26.5625MHz
Output Frequencies
106.25MHz (Default)
212.5MHz
B
LOCK
D
IAGRAM
OE
FREQ_SEL
(Pullup)
(Pulldown)
P
IN
A
SSIGNMENT
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
GND
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
÷3
1
Q
ICS840001I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
÷6
0
M = ÷24 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
IDT™ / ICS™
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
1
1
ICS840001I
PRELIMINARY
ICS840001I
Circuit
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Integrated
ICS840001I
Systems, Inc.
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
TSD
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
FREQ_SEL
GN D
Q
V
DD
Power
Input
Input
Input
Power
Output
Power
Type
Description
Analog supply pin.
Output enable pin. When HIGH, Q output is enabled.
Pullup
When LOW, forces Q to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω typical output impedance.
Core supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
V
DD
, V
DDA
= 3.465V
V
DD
, V
DDA
= 2.625V
Test Conditions
Minimum
Typical
4
TBD
TBD
51
51
7
12
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
Output
Q
Hi-Z
Active
840001AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 20, 2005
IDT™ / ICS™
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
2
ICS840001I
PRELIMINARY
ICS840001I
Circuit
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Integrated
ICS840001I
Systems, Inc.
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
TSD
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
75
8
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
73
8
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FREQ_SEL
OE
FREQ_SEL
OE
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V
V
DD
= 2.625V
-5
-150
2.6
1.8
0. 5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= 3.465V or 2.625V
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
840001AGI
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 20, 2005
IDT™ / ICS™
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
3
ICS840001I
PRELIMINARY
ICS840001I
Circuit
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Integrated
ICS840001I
Systems, Inc.
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
TSD
LVCMOS/LVTTL C
LOCK
G
ENERATOR
Minimum
Typical
Fundamental
26.5625
50
7
1
MH z
Ω
pF
mW
Maximum
Units
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
FREQ_SEL = 1
FREQ_SEL = 0
fOUT = 106.25MHz,
(637kHz to 5MHz)
fOUT = 212.5MHz,
(2.55MHz to 20MHz)
20% to 80%
Minimum
186.66
93.33
Typical
212.5
106.25
0.70
0.50
400
50
Maximum
226.66
113.33
Units
MHz
MHz
ps
ps
ps
%
t
jit(Ø)
t
R
/ t
F
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
odc
Output Duty Cycle
All parameters are characterized @ 212.5MHz and 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
FREQ_SEL = 1
FREQ_SEL = 0
fOUT = 106.25MHz,
(637kHz to 5MHz)
fOUT = 212.5MHz,
(2.55MHz to 20MHz)
20% to 80%
Minimum
186.66
93.33
Typical
212.5
106.25
0.70
0.50
450
50
Maximum
226.66
113.33
Units
MHz
MHz
ps
ps
ps
%
t
jit(Ø)
t
R
/ t
F
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
odc
Output Duty Cycle
All parameters are characterized @ 212.5MHz and 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plots following this section.
840001AGI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 20, 2005
IDT™ / ICS™
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
4
ICS840001I
PRELIMINARY
ICS840001I
Circuit
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Integrated
ICS840001I
Systems, Inc.
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
TSD
LVCMOS/LVTTL C
LOCK
G
ENERATOR
➤
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 5MHz = 0.70ps (typical)
T
YPICAL
P
HASE
N
OISE AT
106.25MH
Z
0
-10
-20
-30
-40
-50
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
840001AGI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 20, 2005
IDT™ / ICS™
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
5
ICS840001I
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