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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> LS1026AAN8Q1A
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LS1026AAN8Q1A

Description
Multifunction Peripheral,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB，165 Pages
Manufacturere2v technologies
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LS1026AAN8Q1A Overview

Multifunction Peripheral,

LS1026AAN8Q1A Parametric

Parameter NameAttribute value
Makere2v technologies
Reach Compliance Codecompliant

LS1026AAN8Q1A Preview

LS1046A, LS1026A
QorIQ
Preliminary datasheet DS1202
Features
•
LS1046A has four cores and LS1026A has two cores
•
Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs
–
Arranged as a single cluster of four cores
sharing a single 2 MB L2 cache
–
Up to 1.8 GHz operation
–
Single-threaded cores with 32 KB L1 data cache
and 48 KB L1 instruction cache
•
Additional peripheral interfaces
–
One Quad Serial Peripheral Interface
–
–
–
–
–
–
–
–
–
–
–
(QSPI) controller
One Serial Peripheral Interface (SPI) controller
Integrated flash controller (IFC) supporting
NAND and NOR flash
Three high-speed USB 3.0 controllers
with integrated PHY
One Enhanced Secure Digital Host
Controller supporting SD 3.0, eMMC 4.4,
and eMMC 4.5
Four I2C controllers
Two 16550-compliant DUARTs and six low-
power UARTs (LPUARTs)
General purpose IO (GPIO), eight Flextimers
One Queue Direct Memory Access
Controller (qDMA)
One Enhanced Direct Memory Access
Controller (eDMA)
Global programmable interrupt controller (GIC)
Thermal monitoring unit (TMU)
•
Hierarchical interconnect fabric
–
Up to 700 MHz operation
•
One 32-bit/64-bit DDR4 SDRAM memory controller
with ECC and interleaving support
–
Up to 2.1 GT/s
•
Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following
functions:
–
Packet parsing, classification, and
distribution (FMan)
–
Queue management for scheduling, packet
sequencing, and congestion management
(QMan)
–
Hardware buffer management for buffer
allocation and de-allocation (BMan)
–
Cryptography acceleration (SEC)
–
IEEE 1588™ support
•
780 FC-PBGA package, 23 mm x 23 mm
•
Two RGMII interfaces
•
Eight SerDes lanes for high-speed peripheral
interfaces
–
Three PCI Express 3.0 controllers
–
One Serial ATA (SATA 6 Gbit/s) controller
–
Up to two XFI (10 GbE) interfaces
–
Up to five SGMII interfaces supporting 1000 Mbps
–
Up to three SGMII interfaces supporting 2500
Mbps
–
Up to one QSGMII interface
–
Supports 10GBase-KR
–
Supports 1000Base-KX
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS
accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices
in accordance with information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, FranceHolding Company: Teledyne e2v Semiconductors SAS
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres.
Teledyne e2v Semiconductors SAS 2019
page 1
1202B-HIREL-01/19
LS1046A, LS1026A [Preliminary]
1
INTRODUCTION
The LS1046A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the
reach of the TELEDYNE-E2V value-performance line of QorIQ communications processors. Featuring power-efficient
64-bit Arm® Cortex®-A72 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.8
GHz.
The LS1046A and LS1026A processors are perfectly suited for a range of embedded applications such as enterprise
routers and switches, linecard controllers, network attached storage, security appliances, virtual customer premise
equipment (vCPE), service providers gateways, and single board computers.
This figure shows the block diagram of the chip.
Figure 1. LS1046A block diagram
Arm® Cortex®-A72
32-bit/64-bit Core
32 KB
32 KB
32 KB
D-Cache
D-Cache
D-Cache
32 KB
D-Cache
32 KB
32 KB
48 KB
I-Cache
I-Cache
32 KB
I-Cache
I-Cache
2 MB L2 - C ache
64-bit
DDR4
Memor y Controller
Secure Boot
Trust Zone
Power Management
IFC, QSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
3x USB3.0 w/PHY
Buffer
Manager
1G
1G
1G
Security
Queue
Engine
(SEC)
Manager
CCI-400 ™ Coherency Fabric
SMMUs
Frame Manager
Real Time Deb ug
SATA 3.0
PCIe 3.0
PCIe 3.0
PCIe 3.0
Watchpoint
Cross
Trigger
Perf
Monitor
Parse, classify,
distribute
1G
1G
1/2.5/1 0G
1/2.5/1 0G
1/2.5G
Trace
DPAA Hardware
4-Lane 10 GHz SerDes
6x LPUART
Core Complex
Accelerators and Memor y Control
Basic Peripherals, Interconnect, and Deb ug
Networking Elements
4-Lane 10 GHz SerDes
1202A-HIREL-01/19
page 2
Teledyne e2v Semiconductors SAS 2019
LS1046A, LS1026A [Preliminary]
Figure 2. LS1026A block diagram
Arm® Cortex®-A72
32-bit/64-bitCore
32 KB
32 KB
32 KB
D-Cache
D-Cache
D-Cache
32 KB
D-Cache
32 KB
32 KB
48 KB
I-Cache
I-Cache
32 KB
I-Cache
I-Cache
ache
2 MB L2 - C
Secur e Boot
64-bit
DDR4
Memory Controller
Trust Zone
Power Management
IFC, QSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
Y
3x USB3.0 w/PH
Secur ity
Engine
(SEC)
CCI-400™ Coherency Fabric
SMMUs
Frame Manager
PCIe 3.0
SATA 3.0
PCIe 3.0
PCIe 3.0
Queue
Manager
Real Time Debug
Watchpoint
Cross
Trigger
Perf
Trace
Monitor
,
Parse, classify
distribute
1G 1G
1/2.5/10G
Buffer
Manager 1G 1G
1/2.5/10G
1/2.5G
1G
DPAA Hardware
4-Lane 10 GHz SerDes
4-Lane 10 GHz SerDes
6x LPUART
Core Complex
y
Accelerators and Memor Control
ug
Basic Peripherals, Interconnect, and Deb
Networking Elements
Teledyne e2v Semiconductors SAS 2019
page 3
1202B-HIREL-01/19
LS1046A, LS1026A [Preliminary]
2
2.1
PIN ASSIGNMENTS
780 BGA ball layout diagrams
This figure shows the complete view of the LS1046A BGA ball map diagram. Figure 4, Figure 5, Figure 6, and Figure 7
show quadrant views.
Figure 3. Complete BGA Map for the LS1046A
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
1
2
3
4
5
6
7
8
9
0 1
1 1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
3
4
5
6
7
8
9
0 1
1 1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
B
C
D
E
SEE DETAIL A
SEE DETAIL B
F
G
H
J
K
L
M
N
P
R
T
U
V
W
SEE DETAIL C
SEE DETAIL D
Y
AA
AB
AC
AD
AE
AF
AG
AH
DDRC1
IFC
DUART
I2C
eSPI
eSDHC
Interrupts
Battery Backed Trust
Trust
System Control
ASLEEP
SYSCLK
DDR Clocking
RTC
Debug
DFT
JTAG
Analog Signals
Serdes 1
Serdes 2
USB3 PHY 1
USB3 PHY 2
USB PHY 3
Ethernet MI 1
Ethernet MI 2
EC1
EC2
USB
DIFF_SYSCLK
Power
Ground
No Connects
1202B-HIREL-01/19
page 4
Teledyne e2v Semiconductors SAS 2019
LS1046A, LS1026A [Preliminary]
Figure 4. Detail A
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
USB3_
TX_
P
2
GND001
3
USB3_
RX_
P
4
USB3_
RX_
M
5
GND002
6
USB3_
D_
M
7
USB3_
VBUS
IFC_
AD01
8
IFC_
AD03
9
IFC_
AD04
1
0
11
IFC_
AD06
12
IFC_
AD08
13
IFC_
AD09
14
IFC_
AD11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
USB3_
TX_
M
GND004
GND005
USB3_
ID
USB3_
D_
P
GND006
IFC_
AD00
IFC_
AD02
GND007
IFC_
AD05
IFC_
AD07
GND008
IFC_
AD10
GND014
GND015
USB2_
RX_
P
USB2_
RX_
M
GND016
USB2_
D_
M
USB2_
VBUS
IFC_
A17
IFC_
A18
IFC_
A20
IFC_
A21
IFC_
A23
IFC_
A25
IFC_
A27
USB2_
TX_
P
USB2_
TX_
M
GND019
GND020
USB2_
ID
USB2_
D_
P
GND021
IFC_
A16
GND022
IFC_
A19
IFC_
A22
GND023
IFC_
A24
IFC_
A26
GND028
GND029
USB1_
RX_
P
USB1_
RX_
M
GND030
USB1_
D_
M
USB1_
VBUS
EVT2_B
ASLEEP
EVT0_B
EVT4_B
EVT3_B
EVT1_B
IFC_
TE
USB1_
TX_
P
USB1_
TX_
M
GND033
GND034
USB1_
ID
USB1_
D_
P
GND035
HRESET_ PORESET_
B
B
RESET_
REQ_B
IRQ00
NC_
F12
PROG_
MTR
GND036
GND040
GND041
USB1_
RESREF
USB2_
RESREF
USB3_
RESREF
USB_
PWRFAULT
EVT9_B
TH_
VDD
GND042
GND043
GND044
TA_BB_
VDD
TA_
PROG_
SFP
SYSCLK
UART1_
SOUT
UART1_
SIN
GND047
GND048
GND049
USB_
DRVVBUS
IRQ02
TH_
TPA
AVDD_
PLAT
AVDD_
CGA2
AVDD_
CGA1
TA_BB_
TD1_
TMP_
DETECT_B CATHODE
GND050
UART1_
CTS_B
UART1_
RTS_B
IRQ03
IRQ04
IRQ05
GND057
GND058
GND059
GND060
GND061
GND062
GND063
TD1_
ANODE
OVDD1
UART2_
SIN
GND067
IIC2_
SCL
GND068
IRQ06
GND069
USB_
SVDD1
USB_
HVDD1
NC_
K9
NC_
K10
NC_
K11
NC_
K12
GND070
VDD01
UART2_
RTS_B
UART2_
SOUT
IIC2_
SDA
IIC3_
SCL
IRQ07
GND075
USB_
SVDD2
USB_
HVDD2
NC_
L9
GND076
VDD05
GND077
VDD06
GND078
IIC1_
SDA
UART2_
CTS_B
IIC4_
SCL
IIC3_
SDA
IRQ08
GND084
USB_
SDVDD1
USB_
SDVDD2
GND085
VDD10
GND086
VDD11
GND087
VDD12
IIC1_
SCL
GND093
IIC4_
SDA
GND094
IRQ09
GND095
DVDD1
GND096
VDD15
GND097
VDD16
GND098
VDD17
GND099
SDHC_
DAT0
SDHC_
CMD
SDHC_
CLK
IRQ10
NC_
P5
GND105
DVDD2
NC_
P8
GND106
VDD21
GND107
VDD22
GND108
VDD23
1
2
3
4
5
6
7
8
9
0
1
11
12
13
14
DDRC1
IFC
DUART
I2C
eSPI
eSDHC
Interrupts
Battery Backed Trust
Trust
System Control
ASLEEP
SYSCL K
DDR Clocking
RTC
Debug
DFT
JTA G
Analog Signals
Serdes 1
Serdes 2
USB3 PHY 1
USB3 PHY 2
USB PHY 3
Ethernet MI 1
Ethernet MI 2
EC1
EC2
USB
DIFF_SYSCL K
Powe r
Ground
No Connects
Teledyne e2v Semiconductors SAS 2019
page 5
1202B-HIREL-01/19
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Reach Compliance Code compliant compliant compliant compli

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