Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8Mx3
nOUT
OUT
V
CC
Crystal Oscillator:
LVPECL C
LOCK
O
UTPUT
ICS8Mx3
L
OW
J
ITTER
, H
IGH
F
REQUENCY
X
TAL
O
SCILLATOR
•
(including initial accuracy, operating temperature variation,
supply voltage variation, load variation, reflow drift, and aging for 10 years)
Low phase jitter < 1 ps rms maximum
(12kHz to 20MHz)
6-pin CERHERMETIC 5 x 7 x 1.5mm SMT
E
LECTRICAL
S
PECIFICATIONS
Unless stated otherwise, V
CC
= 2.5 Volts + 5% or 3.3 Volts + 5%, T
A
= 0
o
C to +70
o
C (commercial), T
A
= -40
o
C to +85
o
C (industrial)
Parameter
Min
Typ
Max
Unit
Conditions
DC
C
HARACTERISTICS
Power Supply Voltage
V
CC
3.135
3.3
3.465
V
3.3V operation
Power Supply
2.375
2.5
2.625
V
2.5V operation
in
8MJ3 and 8MK3 only
(V
CC
, V
EE
pins)
Power Supply Current
I
EE
75
mA
OE
= V
CC
Current with Output Disable
Input Capacitance
Input High Voltage
Output Enable
Input Low Voltage
(OE pin)
LVCMOS/LVTTL
Input High Current
Input Low Current
Internal Pull-up Resistor
Clock Output
Level
(OUT, nOUT)
LVPECL
Output High Voltage
1
Output Low Voltage
1
Peak-to-Peak Output Voltage
Swing
I
OED
C
IN
V
IH
V
IL
I
IH
I
IL
R
PULLUP
V
OH
V
OL
V
SWING
V
CC
-
1.4
V
CC
-
2.0
0.6
75
∆f/f
O
odc
t
R
t
F
t
OSC
50
600
600
10
-150
51
V
CC
-
0.9
V
CC
-
1.7
1.0
750
±100
±50
Output Duty Cycle
Output Rise Time
Output Fall Time
Oscillator Start-up Time
0.7 x
V
CC
5
4
<0.6
mA
pF
V
0.3 x
V
CC
V
µA
µA
kΩ
V
V
V
MHz
ppm p-p
ppm p-p
%
ps
ps
ms
20%
to
80%
of V
OH
- V
OL
20%
to
80%
of V
OH
- V
OL
in 8MH3 and 8MK3
in 8MG3 and 8MJ3
Outputs terminated with
50Ω
to V
CC
- 2V.
See P
ARAMETER
M
EASUREMENT
I
NFORMATION
, Output
Load AC Test Circuit diagrams.
See P
ARAMETER
M
EASUREMENT
I
NFORMATION
,
Output Rise and Fall Time diagram.
OE
= G
ND
V
CC
= V
IN
= 2.625 or 3.465V
V
CC
= 2.625 or 3.465V,
V
IN
= 0V
AC
C
HARACTERISTICS
Output Frequency Range
Output
Frequency Stability error
(OUT, nOUT)
All conditions
Includes frequency set,
V
CC
,
T
A
& load variation,
reflow drift, 10 yr. aging
See
Output Duty Cycle diagram
and Rise and Fall Time diagram
in P
ARAMETER
M
EASUREMENT
I
NFORMATION
.
Time at Min. V
CC
(3.135V or 2.375V) to be 0s
(design target)
Deterministic
Random
Root Mean Square
Peak to Peak
Accumulated Jitter
n = 2 to 50,000 cycles
σ
of Random jitter
σ
of Total jitter distribution
RMS Phase Jitter, (Random)
2
t
jit(Ø)
Jitter
t
DS
t
RS
t
RMS
t
P
-
P
t
acc
2
3
3
3
3
<1
ps rms
design target
0.2
3
3
25
4
ps
ps
ps
ps
ps
Note 1: Outputs terminated with 50Ω to
V
CC
- 2V.
See P
ARAMETER
M
EASUREMENT
I
NFORMATION
, Output Load AC Test Circuit diagrams.
Note 2: Measured using an Aeroflex PN9500 with a 12 kHz to 20MHz integration range.
Note 3: Measured using a Wavecrest SIA-3000.
S
UPPLY
V
OLTAGE
& F
REQUENCY
A
CCURACY
G
H
J
K
=
=
=
=
3.3V
3.3V
2.5V / 3.3V
2.5V / 3.3V
±50
ppm
±
100 ppm
±
50 ppm
±
100 ppm
ICS8Mx3 Datasheet Rev A
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
Revised 30Nov2004
Networking & Communications
●
w w w. i c s t . c o m
●
tel (508) 852-5400
V
EE
OE
NC
•
Stable, ultra low jitter, LVPECL clock generation
•
For Gigabit Ethernet, Fibre Channel, PCI-Express,
other applications
•
Clock output frequencies from 75 to 750 MHz
•
One differential LVPECL clock output
•
Output Enable
(OE)
pin
(tri-state – with ultra low current – when low)
•
Small 6-pin 5 x 7 x 1.5mm SMT ceramic package
•
Low profile package allows back-side PCB mounting
•
Pb-free RoHS compliant (by default; no additional code required)
•
2.5V or 3.3V device power supply options
•
Commercial
(0 to +70 C) and
Industrial
(-40 to +85 C)
temperatures
•
Frequency stability of ±50 or ±100 ppm
O
O
6
8 M x3
(Top View)
2
5
3
1
4
Integrated
Circuit
Systems, Inc.
P
IN
D
ESCRIPTIONS
1
2
3
4
5
6
OE
NC
V
EE
OUT
nOUT
V
CC
Input
Unused
Power
Output
Power
No internal terminator
Internal pull-up resistor
Output enable pin. Tri-state – with
ultra low current – when low.
LVCMOS/LVTTL interface levels.
No connect.
Negative supply pin.
Differential clock output connections.
LVPECL interface levels.
Power supply pin.
ICS8M
X
3
Crystal Oscillator:
LVPECL C
LOCK
O
UTPUT
PRELI MINARY
Inputs
Outputs
Positive Supply Voltage
Package Thermal Impedence
Storage Temperature
T
S
A
BSOLUTE
M
AXIMUM
R
ATINGS
V
I
-
0.5
to V
CC
+
0.5
V
O
V
CC
-
0.5
to V
CC
+
0.5
4.6
TBD
V
V
V
°C/W (0 lfpm)
o
-
40
to +
100
C
For typical value of internal pull-up resistor, see DC Characteristics
.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed in DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
2V
V
CC
Qx
SCOPE
V
CC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
V
EE
V
EE
-1.3V ± 0.165V
3.3V Output Load AC Test Circuit
-0.5V ± 0.125V
2.5V Output Load AC Test Circuit
nOUT
Phase Noise Plot
Noise Power
OUT
t
PW
(Output Pulse Width)
t
PERIOD
odc =
t
PW
t
PERIOD
Output Duty Cycle / Pulse WIdth / Period
80%
80%
V
SWING
20%
f
1
Offset Frequency
f
2
Clock
Outputs
20%
t
R
t
F
RMS Jitter = Area Under Offset Frequency Markers
RMS Phase Jitter
Output Rise and Fall Time
ICS8Mx3 Datasheet Rev A
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
2 of 4
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●
Revised 30Nov2004
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●
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Integrated
Circuit
Systems, Inc.
A
PPLICATION
I
NFORMATION
T
ERMINATION FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termination for 3.3V LVPECL
outputs. The two different layouts mentioned are recommended only as guide-
lines.
OUT and nOUT are low impedance follower outputs that generate ECL/LVPECL
compatible outputs. Therefore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These outputs are designed to
drive 50W transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and
1B
show two different layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed circuit and clock
component process variations.
ICS8M
X
3
Crystal Oscillator:
LVPECL C
LOCK
O
UTPUT
PRELI MINARY
T
ERMINATION FOR
2.5V LVPECL O
UTPUT
Figure 2A
and
Figure 2B
show examples of termination for 2.5V LVPECL driver.
These terminations are equivalent to terminating 50Ω to V
CC
- 2V.
For V
CC
= 2.5V, the V
CC
- 2V is very close to ground level. The R3 in Figure 2B
can be eliminated and the termination is shown in
Figure 2C.
2.5V
VCC=2.5V
Zo = 50 Ohm
2.5V
R1
250
R3
250
+
Zo = 50 Ohm
-
Z
o
= 50Ω
FOUT
FIN
2.5V
LVPECL
2,5V
Driv er
Driver
R2
62.5
R4
62.5
Z
o
= 50Ω
50Ω
1
RTT =
Z
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
o
50Ω
Figure 2A: 2.5V LVPECL Driver Termination Example
VCC=2.5V
2.5V
V
CC
- 2V
RTT
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Figure 1A: 3.3V LVPECL Output Termination
3.3V
125Ω
Z
o
= 50Ω
FOUT
FIN
125Ω
2.5V
2,5V LVPECL
Driv er
Driver
R1
50
R2
50
R3
18
Figure 2B: 2.5V LVPECL Driver Termination Example
VCC=2.5V
2.5V
Z
o
= 50Ω
84Ω
84Ω
Zo = 50 Ohm
+
Figure 1B: 3.3V LVPECL Output Termination
2.5V LVPECL
2,5V
Driver
Driv er
Zo = 50 Ohm
-
R1
50
R2
50
Figure 2C: 2.5V LVPECL Termination Example
ICS8Mx3 Datasheet Rev A
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
3 of 4
Networking & Communications
●
Revised 30Nov2004
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●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
ICS8M
X
3
Crystal Oscillator:
LVPECL C
LOCK
O
UTPUT
PRELI MINARY
D
EVICE
P
ACKAGE
O
UTLINE
-
6-pin, 5 x 7 x 1.5mm SMT CERHERMETIC
SYMBOL
DIMENSION IN MM
NOMINAL TOLERANCE
A
B
C
D
1
D
2
E
F
G
H
J
5
7
1.5
2.54
5.08
2.6
0.6
1.4
0.15 Ref.
0.65 Ref.
± 0.15
± 0.15
± 0.15
± 0.13
± 0.13
± 0.13
± 0.13
± 0.13
_
_
Device Package Outline
O
RDERING
I
NFORMATION
Part Number:
Device
Supply Voltage & Frequency Accuracy
ICS8M
x
3 -fff.fff
r p t u
G=
H=
J=
K=
3.3V
3.3V
2.5/3.3V
2.5/3.3V
±
50 ppm
±100
ppm
±
50 ppm
±100
ppm
E
XAMPLE
O
UTPUT
F
REQUENCIES
75.000
100.000
106.250
125.000
150.000
155.520
156.250
187.500
200.000
212.500
250.000
311.040
312.500
500.000
600.000
622.080
625.000
750.000
Consult ICS for the availability of other frequencies
E
XAMPLE
P
ART
N
UMBERS
Part/Order Number
For option ...
Marking
3.3 V
106.25 MHz
(blank)
Commercial
±50 ppm
Output Type
3 = LVPECL
Output Frequency (MHz)
Leading zeroes dropped. Fourth decimal place added if
necessary. See Standard Output Frequencies on right.
Consult ICS for other frequencies.
Revision of Product
A = Initial Release
Package Type (individual devices)
J = 5x7mm ceramic SMT
Ambient Temperature Range
ICS8MG3-106.250AJ
8MG3-106.250
(blank)
Tube (60 per tube)
2.5/3.3 V
625.00 MHz
±100 ppm
none = commercial = 0 to +70
o
C
I
= industrial = -40 to +85
o
C
none = tube (60 devices per tube)
T = tape and reel (1000 devices)
Bulk Packaging option
ICS8MK3-625.000AJ
I
T
8MK3-625.000
Industrial
Tape & Reel
(1000)
Note: Lead-free by default (no additional “LF” code needed)
(Pb-free and RoHS compliant)
ICS8Mx3 Datasheet Rev A
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
4 of 4
Networking & Communications
●
Revised 30Nov2004
w w w. i c s t . c o m
●
tel (508) 852-5400
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