Qormino QT1040
Qormino Integrated Multicore
Communications Processor with DDR3L
Datasheet Preliminary DS1168
FEATURES
•
e5500 cores built on Power Architecture
®
technology,
– QT1040 has four cores and T1020 has two cores
– Each core with a private 256KB L2 cache
– 1GB DDR3L with ECC
256 KB shared L3 CoreNet platform cache (CPC)
Hierarchical interconnect fabric
– CoreNet Coherency manager supporting coherent and non‐
coherent transactions with prioritization and bandwidth
allocation amongst CoreNet end‐points
– 150Gbps coherent read bandwidth
Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
– Packet parsing, classification, and distribution
– Queue management for scheduling, packet sequencing, and
congestion management
– Hardware buffer management for buffer allocation and de‐
allocation
– Cryptography Acceleration
– RegEx Pattern Matching Acceleration
– IEEE Std 1588
™
support
Integrated 8‐port Gigabit Ethernet switch
– 8K MAC addresses, 4K VLANs
– Static Address provisioning
– Dynamic learning of MAC addresses and aging
– Policing with storm control and MC/BC protection
– Link aggregation (IEEE Std 802.3ad)
– Spanning Tree Protocol (STP, RSTP and MSTP)
– Access Control List
– VLAN editing, translation and remarking
– Hierarchical QoS with DWRR scheduling
Parallel Ethernet interfaces
– Up to two RGMII interface
– One MII interface
Eight SerDes lanes for high‐speed peripheral interfaces
– Four PCI Express 2.0 controllers
– Two Serial ATA (SATA 3Gb/s) controllers
– Up to two QSGMII interface
– Up to six SGMII interface supporting 1000 Mbps
– Supports 1000Base‐KX
•
Additional peripheral interfaces
– Two high‐speed USB 2.0 controllers with integrated PHY
– Enhanced secure digital host controller with support for
high capacity memory card (SD/eSDHC/eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Two DUARTs
– Integrated flash controller supporting NAND and NOR flash
– Display interface unit (DIU) with 12‐bit dual data rate
– TDM Interface
– Four GPIO controllers supporting up to 109 general purpose
I/O signals
– Two 8‐channel DMA engines
– Multicore programmable interrupt controller (MPIC)
•
QUICC Engine block
– 32‐bit RISC controller for flexible support of the
communications peripherals
– Serial DMA channel for receive and transmit on all serial
channels
– Two universal communication controllers, supporting TDM,
HDLC and UART
•
878 FC‐PBGA package, 25 mm × 38 mm
•
•
•
•
OVERVIEW
The QT1040 Qormino advanced multicore processor combines four
64‐bit ISA Power Architecture
™
processor cores with high‐perfor‐
mance data path acceleration and network and peripheral bus
interfaces required for networking, telecom/datacom, wireless
infrastructure, and military/aerospace applications.
This chip can be used for combined control, data path, and applica‐
tion layer processing in routers, switches, gateways, and general‐
purpose embedded computing systems. Its high level of integration
offers significant performance benefits compared to multiple dis‐
crete devices, while also simplifying board design.
This figure shows the block diagram of the chip.
•
•
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any
use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its
standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with information contained
herein.
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc
Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
Contact e2v by e‐mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.
© e2v technologies (uk) limited 2016
1168A–HIREL–07/16
QT1040 ‐ [Preliminary]
1.
BLOCK DIAGRAM
QT1040 Block diagram
Figure 1‐1.
2
1168A–HIREL–07/16
© e2v technologies (uk) limited 2016
QT1040 ‐ [Preliminary]
2.
2.1
PIN ASSIGNMENTS
780 ball layout diagrams
This figure shows the complete view of the QT1040 ball map diagram. Figure 2‐2, Figure 2‐3, Figure 2‐4, and Fig‐
ure 2‐5 show quadrant views.
Figure 2‐1.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
1
GND
Complete BGA Map for the QT1040
4
IFC_AD00
2
GND
3
IRQ_OUT_B
5
IFC_AD02
6
IFC_AD04
7
IFC_AD05
8
IFC_AD07
9
IFC_AD09
10
IFC_AD10
11
IFC_AD12
12
IFC_AD14
13
IFC_AD15
14
IFC_BCTL
15
IFC_RB1_
B
16
IFC_NDD
QS
17
IFC_CLK0
18
TDI
19
IFC_CLK1
20
GND
21
GND
22
G1VDD
23
GND
24
G1VDD
25
GND
26
G1VDD
27
GND
28
G1VDD
29
GND
30
G1VDD
31
GND
32
G1VDD
33
GND
34
G1VDD
35
GND
36
G1VDD
37
GND
38
G1VDD
39
GND
40
G1VDD
41
GND
42
G1VDD
43
GND
44
G1VDD
A
B
C
D
E
F
G
H
J
K
L
M
N
ASLEEP
RESET_RE
Q_B
GND
IFC_AD01
IFC_AD03
GND
IFC_AD06
IFC_AD08
GND
IFC_AD11
IFC_AD13
GND
IFC_TE
IFC_RB0_
B
GND
RTC
TMS
GND
FA_ANAL
OG_PIN
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
EVT2_B
EVT3_B
EVT4_B
EVT1_B
IFC_A16
IFC_A17
IFC_A19
IFC_A21
IFC_A23
IFC_A25
IFC_A27
IFC_A29
IFC_CS0_
B
IFC_PAR1
IFC_PAR0
IFC_CS3_
B
IFC_CS5_
B
TDO
IFC_CS7_
B
FA_ANAL
OG_G_V
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
IRQ03
GND
IRQ01
IRQ04
IRQ05
EVT0_B
IFC_A18
IFC_A20
IFC_A22
IFC_A24
IFC_A28
IFC_A30
IFC_WE0_
B
IFC_NDDD
R_CLK
IFC_OE_B
IFC_CS2_
B
IFC_AVD
IFC_CS6_
B
TRST_B
GND
GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
USB_AGN
D
USB_AGN
D
USB_AGN
D
USB1_VB
USCLMP
GND
CLK_OUT
GND
HRESET_B
IRQ02
GND
IFC_A26
IFC_A31
GND
IFC_PERR
_B
IFC_CS1_
B
GND
IFC_CS4_
B
TCK
GND
AVDD_D1
TD1_ANO
DE
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
USB1_UD
P
USB1_UD
M
USB_AGN
D
USB1_UID
USB1_PW
RFAULT
USB1_DR
VVBUS
IRQ00
USBCLK
SCAN_MO
DE_B
GND
GND
PROG_SF
P
PORESET_
B
DIFF_SYSC
LK_B
GND
IFC_CLE
IFC_WP0_
B
CKSTP_O
UT_B
TMP_DET
ECT_B
D1_MVRE
F
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
G1VDD
USB_AGN
D
USB_AGN
D
SEE DETAIL A
USB_AGN
D
USB_IBIAS
_REXT
USB_AGN
D
GND
GND
TEST_SEL
_B
TH_VDD
AVDD_PL
AT
AVDD_CG
A1
AVDD_CG
A2
GND
DIFF_SYSC
LK
SYSCLK
GND
GND
SEE DETAIL B
GND
SENSEVD
D
SENSEGN
D
TD1_CAT
HODE
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
USB2_UD
P
USB2_UD
M
USB_AGN
D
USB2_UID
USB2_PW
RFAULT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
USB_AGN
D
USB_AGN
D
USB_AGN
D
USB2_VB
USCLMP
USB2_DR
VVBUS
GND
GND
USB_HVD
D
USB_OVD
D
USB_OVD
D
O1VDD
O1VDD
O1VDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
GND
DDRCLK
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
SDHC_CLK
GND
SDHC_CM
D
SDHC_DA
T1
GND
GND
GND
USB_HVD
D
USB_SVD
D
USB_SVD
D
VDDC
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
SDHC_D
A
T3
SDHC_DA
T0
SDHC_DA
T2
IRQ10
SDHC_CD
_B
NC01
GND
EVDD
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
GND
RESET#
SPI_CS0_
B
SPI_CS1_
B
SPI_CS2_
B
CLK12
SDHC_WP
NC02
GND
CVDD
GND
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
SPI_CLK
GND
SPI_CS3_
B
CLK11
GND
GND
GND
DVDD
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
SPI_MISO
SPI_MOSI
CLK10
CLK09
DMA1_DR
EQ0_B
NC03
GND
DVDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
TDMA_TS
YNC
TDMA_RQ
TDMB_TS
YNC
TDMB_RQ
DMA1_D
DONE0_B
NC04
GND
DVDD
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
SEE DETAIL E
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
TDMA_TX
D
GND
TDMB_RS
YNC
TDMB_TX
D
GND
GND
GND
L1VDD
GND
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
TDMA_RS
YNC
TDMA_RX
D
IRQ11
TDMB_RX
D
DMA1_DA
CK0_B
GND
GND
L1VDD
GND
VDDC
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
DDR_VTT
DDR_VTT
IIC1_SDA
IIC3_SCL
IIC2_SCL
UART2_R
TS_B
DMA2_DR
EQ0_B
GND
GND
LVDD
GND
GND
VDDC
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
DDR_VTT
DDR_VTT
IIC1_SCL
GND
IIC3_SDA
UART2_SI
N
GND
GND
GND
LVDD
GND
VDDC
GND
VDDC
GND
VDD
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
G1VDD
G1VDD
UART1_R
TS_B
UART1_C
TS_B
IIC2_SDA
UART2_C
TS_B
DMA2_D
DONE0_B
GND
GND
GND
GND
GND
GND
GND
S1VDD
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
SD1_IMP_
CAL_TX
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
G1VDD
UART1_SI
N
UART1_S
OUT
IIC4_SCL
UART2_S
OUT
DMA2_DA
CK0_B
GND
GND
GND
GND
GND
GND
SD1_IMP_
CAL_RX
S1GND
SD1_REF_
CLK1_N
S1GND
AGND_SD
1_PLL1
S1GND
SD1_REF_
CLK2_N
S1GND
AGND_SD
1_PLL2
S1GND
G1VDD
GND
G1VDD
GND
G1VDD
G1VDD
G1VDD
IRQ08
GND
EC1_COL
EC1_RX_E
R
SEE DETAIL C
IIC4_SDA
IRQ06
GND
TSEC_158
8_TRIG_I
N1
GND
GND
SENSEVD
DC
SENSEGN
DC
GND
GND
S1GND
SD1_REF_
CLK1_P
S1GND
AVDD_SD
1_PLL1
S1GND
EC1_TXD3
EC1_TX_E
R
IRQ09
EC2_GTX_
CLK125
TSEC_158
8_ALARM
_OUT2
SEE DETAIL D
SD1_REF_
CLK2_P
S1GND
AVDD_SD
1_PLL2
S1GND
GND
X1VDD
X1GND
X1GND
X1VDD
G1VDD
X1GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
TSEC_158
8_CLK_IN
X1VDD
X1GND
X1GND
X1VDD
X1GND
X1GND
X1VDD
X1GND
X1GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
EC1_RX_C
LK
EC1_RXD3
EC1_TXD2
GND
IRQ07
GND
TSEC_158
8_CLK_O
UT
TSEC_158
8_PULSE_
OUT2
X1GND
SD1_TX0_
P
SD1_TX1_
P
X1GND
SD1_TX2_
P
SD1_TX3_
P
X1GND
SD1_TX4_
P
SD1_TX5_
P
SD1_TX6_
P
SD1_TX7_
P
X1GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
EC1_RXD2
GND
EC1_TXD0
EC1_TXD1
TSEC_158
8_TRIG_I
N2
TSEC_158
8_PULSE_
OUT1
EC2_TXD0
EC2_GTX_
CLK
X1GND
SD1_TX0_
N
SD1_TX1_
N
X1GND
SD1_TX2_
N
SD1_TX3_
N
X1GND
SD1_TX4_
N
SD1_TX5_
N
X1GND
SD1_TX6_
N
SD1_TX7_
N
X1GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
EC1_RXD1
EC1_RXD0
EC1_GTX_
CLK
EC1_TX_C
TL
TSEC_158
8_ALARM
_OUT1
EC2_TXD2
EC2_TXD1
EC2_TX_C
TL
GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
S1GND
GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
AF
AG
AH
GND
EC1_RX_C
TL
EC1_GTX_
CLK125
GND
EC2_TXD3
GND
EC2_RXD1
EC2_RX_C
TL
S1GND
SD1_RX0_
N
SD1_RX1_
N
S1GND
SD1_RX2_
N
SD1_RX3_
N
S1GND
SD1_RX4_
N
SD1_RX5_
N
S1GND
SD1_RX6_
N
SD1_RX7_
N
S1GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
EMI1_MD
C
EMI1_MD
IO
EC2_RX_C
LK
EC2_RXD3
EC2_RXD2
EC2_RXD0
S1GND
SD1_RX0_
P
SD1_RX1_
P
S1GND
SD1_RX2_
P
SD1_RX3_
P
S1GND
SD1_RX4_
P
SD1_RX5_
P
S1GND
SD1_RX6_
P
SD1_RX7_
P
S1GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
Power
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Analog Signals
DDR Clocking
DDR SDRAM Memory Interface
Debug
DFT
DMA
DIFF_SYSCLK
DUART
eSDHC
eSPI Interface
Ethernet controller 1
and GPIO
Ethernet controller 2
and GPIO
Ethernet Management
Interface
1
GND
I2C
IEEE1588
Integrated Flash
Controller
JTAG
Serdes 1
SYSCLK
System Control
Trust
USB Clocking
USB PHY 1 & 2
DDR VTT
ASLEEP
Programmable Interrupt
Controller
QE_TDM
RTC
3
1168A–HIREL–07/16
© e2v technologies (uk) limited 2016
QT1040 ‐ [Preliminary]
Figure 2‐2.
Detail A
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
GND
2
GND
3
IRQ_OUT_
B
4
IFC_AD00
5
IFC_AD02
6
IFC_AD04
7
IFC_AD05
8
IFC_AD07
9
IFC_AD09
10
IFC_AD10
11
IFC_AD12
12
IFC_AD14
13
IFC_AD15
14
IFC_BCTL
ASLEEP
RESET_RE
Q_B
GND
IFC_AD01
IFC_AD03
GND
IFC_AD06
IFC_AD08
GND
IFC_AD11
IFC_AD13
GND
IFC_TE
EVT2_B
EVT3_B
EVT4_B
EVT1_B
IFC_A16
IFC_A17
IFC_A19
IFC_A21
IFC_A23
IFC_A25
IFC_A27
IFC_A29
IFC_CS0_
B
IFC_PAR1
IRQ03
GND
IRQ01
IRQ04
IRQ05
EVT0_B
IFC_A18
IFC_A20
IFC_A22
IFC_A24
IFC_A28
IFC_A30
IFC_WE0_
B
IFC_NDDD
R_CLK
USB_AGN
D
USB_AGN
D
USB_AGN
D
USB1_VB
USCLMP
GND
CLK_OUT
GND
HRESET_B
IRQ02
GND
IFC_A26
IFC_A31
GND
IFC_PERR
_B
USB1_UD
P
USB1_UD
M
USB_AGN
D
USB1_UID
USB1_PW
RFAULT
USB1_DR
VVBUS
IRQ00
USBCLK
SCAN_MO
DE_B
GND
GND
PROG_SF
P
PORESET_
B
DIFF_SYS
C
LK_B
USB_AGN
D
USB_AGN
D
USB_AGN
D
USB_IBIAS
_REXT
USB_AGN
D
GND
GND
TEST_SEL
_B
TH_VDD
AVDD_PL
AT
AVDD_CG
A1
AVDD_CG
A2
GND
DIFF_SYS
C
LK
USB2_UD
P
USB2_UD
M
USB_AGN
D
USB2_UID
USB2_PW
RFAULT
GND
GND
GND
GND
GND
GND
GND
GND
GND
USB_AGN
D
USB_AGN
D
USB_AGN
D
USB2_VB
USCLMP
USB2_DR
VVBUS
GND
GND
USB_HVD
D
USB_OVD
D
USB_OVD
D
O1VDD
O1VDD
O1VDD
OVDD
SDHC_CLK
GND
SDHC_CM
D
SDHC_DA
T1
GND
GND
GND
USB_HVD
D
USB_SVD
D
USB_SVD
D
VDDC
GND
VDDC
GND
SDHC_D
A
T3
SDHC_DA
T0
SDHC_DA
T2
IRQ10
SDHC_CD
_B
NC01
GND
EVDD
GND
VDDC
GND
VDD
GND
VDD
SPI_CS0_
B
SPI_CS1_
B
SPI_CS2_
B
CLK12
SDHC_WP
NC02
GND
CVDD
GND
GND
VDDC
GND
VDD
GND
SPI_CLK
GND
SPI_CS3_
B
CLK11
GND
GND
GND
DVDD
GND
VDDC
GND
VDD
GND
VDD
SPI_MISO
SPI_MOSI
CLK10
CLK09
DMA1_DR
EQ0_B
NC03
GND
DVDD
GND
GND
VDD
GND
VDD
GND
Analog Signals
DIFF_SYSCLK
Ethernet Management Interface 1
Serdes 1
DDR Clocking
DUART
GND
SYSCLK
DDR SDRAM Memory Interface
eSDHC
I2C
System Control
Debug
eSPI Interface
IEEE1588
Trust
DFT
Ethernet controller 1 and GPIO
Integrated Flash Controller
USB Clocking
DMA
Ethernet controller 2 and GPIO
JTAG
USB PHY 1 & 2
NC
Power
ASLEEP
DDR VTT
Programmable Interrupt Controller
QE_TDM
RTC
4
1168A–HIREL–07/16
© e2v technologies (uk) limited 2016
QT1040 ‐ [Preliminary]
Figure 2‐3.
Detail B
15
IFC_RB1_
B
16
IFC_NDD
QS
17
IFC_CLK0
18
TDI
19
IFC_CLK1
20
GND
21
GND
22
G1VDD
23
GND
24
G1VDD
25
GND
26
G1VDD
27
GND
28
G1VDD
IFC_RB0_
B
GND
RTC
TMS
GND
FA_ANAL
OG_PIN
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
IFC_PAR0
IFC_CS3_
B
IFC_CS5_
B
TDO
IFC_CS7_
B
FA_ANAL
OG_G_V
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
IFC_OE_B
IFC_CS2_
B
IFC_AVD
IFC_CS6_
B
TRST_B
GND
GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
IFC_CS1_
B
GND
IFC_CS4_
B
TCK
GND
AVDD_D1
TD1_ANO
DE
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
IFC_CLE
IFC_WP0_
B
CKSTP_O
UT_B
TMP_DET
ECT_B
D1_MVRE
F
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
G1VDD
SYSCLK
GND
GND
GND
SENSEVD
D
SENSEGN
D
TD1_CAT
HODE
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
GND
GND
GND
GND
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
OVDD
OVDD
OVDD
OVDD
OVDD
GND
DDRCLK
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
GND
RESET#
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
GND
VDD
GND
VDD
GND
VDD
G1VDD
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
VDD
GND
VDD
GND
VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
G1VDD
GND
Analog Signals
DIFF_SYSCLK
Ethernet Management Interface 1
Serdes 1
DDR Clocking
DUART
GND
SYSCLK
DDR SDRAM Memory Interface
eSDHC
I2C
System Control
Debug
eSPI Interface
IEEE1588
Integrated Flash Controller
Trust
DFT
Ethernet controller 1 and GPIO
USB Clocking
DMA
Ethernet controller 2 and GPIO
JTAG
USB PHY 1 & 2
NC
Programmable Interrupt Controller
Power
ASLEEP
DDR VTT
QE_TDM
C
RT
5
1168A–HIREL–07/16
© e2v technologies (uk) limited 2016
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