Features
•
8-bit Microcontroller Compatible with 8051 Products
•
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 256 x 8 Internal RAM
– External Data/Program Memory Interface
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
– 256 Bytes of Flash Data Memory
– 256-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 3-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Timer/Counters with Clock Out Modes
– Enhanced UART
• Automatic Address Recognition
• Framing Error Detection
• SPI and TWI Emulation Modes
– Programmable Watchdog Timer with Software Reset and Prescaler
Special Microcontroller Features
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– Internal 1.8432 MHz Auxiliary Oscillator
I/O and Packages
– Up to 36 Programmable I/O Lines
– Green (Pb/Halide-free) Packages
• 40-lead PDIP
• 44-lead TQFP/PLCC
• 44-pad VQFN/MLF
– Configurable Port Modes (per 8-bit port)
• Quasi-bidirectional (80C51 Style)
• Input-only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 5.5V V
CC
Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V
– 0 to 25 MHz @ 4.5V–5.5V
•
8-bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT89LP51
AT89LP52
•
•
•
•
3709D–MICRO–12/11
1. Pin Configurations
1.1
40-lead PDIP
(T2) P1.0
(T2 EX) P1.1
P1.2
P1.3
P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
(XTAL2) P4.1
(XTAL1) P4.0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
P4.2 (ALE)
P4.3 (PSEN)
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
1.2
44-lead TQFP
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
*NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
*NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
*NC
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
2
AT89LP51/52
3709D–MICRO–12/11
(WR) P3.6
(RD) P3.7
(XTAL2) P4.7
(XTAL1) P4.6
GND
*NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
AT89LP51/52
1.3
44-lead PLCC
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
*NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
1.4
44-pad VQFN/QFN/MLF
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
*NC
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
MOSI/P1.5
MISO/P1.6
SCK/P1.7
RST
RXD/P3.0
*NC
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
44
43
42
41
40
39
38
37
36
35
34
(WR) P3.6
(RD) P3.7
(XTAL2) P4.7
(XTAL1) P4.6
GND
*NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
18
19
20
21
22
23
24
25
26
27
28
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
*NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
*NC
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
POL
*NC
P4.4/ALE
P4.5/PSEN
P2.7/A15
P2.6/A14
P2.5/A13
WR/P3.6
RD/P3.7
XTAL2/P4.7
XTAL1/P4.6
GND
*NC
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
NOTE:
Bottom pad
should be
soldered to ground
3
3709D–MICRO–12/11
1.5
Pin Description
AT89LP51/52 Pin Description
Pin Number
PDIP
6
VQFN
1
Symbol
P1.5
Type
I/O
I/O
I/O
I/O
I/O
I/O
Description
P1.5:
I/O Port 1
bit
5.
MOSI:
SPI
master-out/slave-in. In UART
SPI
mode this pin is
an
output. During In-
System
Programming, this pin is
an
input.
P1.6:
I/O Port 1
bit
6.
MISO:
SPI
master-in/slave-out. In UART
SPI
mode this pin is
an
input. During In-
System
Programming, this pin is
an
output.
P1.7:
I/O Port 1
bit
7.
SCK:
SPI
Clock. In UART
SPI
mode this pin is
an
output. During In-System
Programming, this pin is
an
input.
RST:
External Reset input (Reset polarity depends on POL pin.
See
“External Reset”
on page 33.).
The RST pin can output
a
pulse when the internal Watchdog reset is
active.
P3.0:
I/O Port 3
bit
0.
RXD:
Serial
Port Receiver Input.
Not internally connected
P3.1:
I/O Port 3
bit
1.
TXD:
Serial
Port Transmitter Output.
P3.2:
I/O Port 3
bit
2.
INT0:
External Interrupt 0 Input or Timer 0 Gate Input.
P3.3:
I/O Port 3
bit
3.
INT1:
External Interrupt 1 Input or Timer 1 Gate Input
P3.4:
I/O Port 3
bit
4.
T1:
Timer/Counter 0 External input or output.
P3.5:
I/O Port 3
bit
5.
T1:
Timer/Counter 1 External input or output.
P3.6:
I/O Port 3
bit
6.
WR:
External memory interface Write
Strobe
(active-low).
P3.7:
I/O Port 3
bit
7.
RD:
External memory interface Read
Strobe
(active-low).
P4.7:
I/O Port 4
bit
7.
XTAL2:
Output from inverting oscillator
amplifier.
It may
be used as a
port pin if the
internal RC oscillator or external clock is
selected as
the clock
source.
P4.6:
I/O Port 4
bit
6.
XTAL1:
Input to the inverting oscillator
amplifier and
internal clock generation circuits.
It may
be used as a
port pin if the internal RC oscillator is
selected as
the clock
source.
Ground
Not internally connected
P2.0:
I/O Port 2
bit
0.
A8:
External memory interface Address
bit 8.
P2.1:
I/O Port 2
bit
1.
A9:
External memory interface Address
bit
9.
P2.2:
I/O Port 2
bit
2.
A10:
External memory interface Address
bit
10.
Table 1-1.
TQFP
1
PLCC
7
2
8
7
2
P1.6
3
9
8
3
P1.7
4
10
9
4
RST
I/O
5
6
7
8
9
10
11
12
13
14
15
16
10
5
6
P3.0
I/O
I
NC
11
12
13
14
7
8
9
10
P3.1
P3.2
P3.3
P3.4
I/O
O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
11
17
15
1
P3.5
12
18
16
12
P3.6
13
19
17
13
P3.7
14
20
18
14
P4.7
15
21
19
15
P4.6
I/O
I
16
17
18
19
20
22
23
24
25
26
20
16
17
GND
I
NC
21
22
23
18
19
20
P2.0
P2.1
P2.1
I/O
O
I/O
O
I/O
O
4
AT89LP51/52
3709D–MICRO–12/11
AT89LP51/52
Table 1-1.
TQFP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AT89LP51/52 Pin Description
Pin Number
PDIP
24
25
26
27
28
29
30
VQFN
21
22
23
24
25
26
27
28
31
32
33
34
35
36
37
38
39
40
29
30
31
32
33
34
35
36
37
38
39
1
2
3
4
5
40
41
42
43
44
P1.0
P1.1
P1.2
P1.3
P1.4
POL
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
VDD
Symbol
P2.3
P2.4
P2.5
P2.6
P2.7
P4.5
P4.4
Type
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
NC
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
NC
I/O
I/O
I/O
I
I/O
I/O
I/O
Description
P2.3:
I/O Port 2
bit
3.
A11:
External memory interface Address
bit
11.
P2.4:
I/O Port 2
bit
5.
A12:
External memory interface Address
bit
12.
P2.5:
I/O Port 2
bit
5.
A13:
External memory interface Address
bit
13.
P2.6:
I/O Port 2
bit
6.
A14:
External memory interface Address
bit
14.
P2.7:
I/O Port 2
bit
7.
A15:
External memory interface Address
bit
15.
P4.5:
I/O Port 4
bit
5.
PSEN:
External memory interface Program
Store
Enable (active-low).
P4.4:
I/O Port 4
bit
4.
ALE:
External memory interface Address Latch Enable.
Not internally connected
POL:
Reset polarity (See
“External Reset” on page 33.)
P0.7:
I/O Port 0
bit
7.
AD7:
External memory interface Address/Data
bit
7.
P0.6:
I/O Port 0
bit
6.
AD6:
External memory interface Address/Data
bit
6.
P0.5:
I/O Port 0
bit
5.
AD5:
External memory interface Address/Data
bit
5.
P0.4:
I/O Port 0
bit
4.
AD4:
External memory interface Address/Data
bit
4.
P0.3:
I/O Port 0
bit
3.
AD3:
External memory interface Address/Data
bit
3.
P0.2:
I/O Port 0
bit
2.
AD2:
External memory interface Address/Data
bit
2.
P0.1:
I/O Port 0
bit
1.
AD1:
External memory interface Address/Data
bit
1.
P0.0:
I/O Port 0
bit
0.
AD0:
External memory interface Address/Data
bit
0.
Supply
Voltage
Not internally connected
P1.0:
I/O Port 1
bit
0.
T2:
Timer 2 External Input or Clock Output.
P1.1:
I/O Port 1
bit
1.
T2EX:
Timer 2 External Capture/Reload Input.
P1.2:
I/O Port 1
bit
2.
P1.3:
I/O Port 1
bit
3.
P1.4:
I/O Port 1
bit
4.
PLCC
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
5
3709D–MICRO–12/11
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