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550WA970M000DG

Description
VCXO, Clock, 10MHz Min, 1417MHz Max, 970MHz Nom
CategoryPassive components    oscillator   
File Size231KB,14 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

550WA970M000DG Overview

VCXO, Clock, 10MHz Min, 1417MHz Max, 970MHz Nom

550WA970M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionDILCC6,.25
Reach Compliance Codeunknown
JESD-609 codee3
Installation featuresSURFACE MOUNT
Number of terminals6
Maximum operating frequency1417 MHz
Minimum operating frequency10 MHz
Nominal operating frequency970 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output low current32 mA
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeDILCC6,.25
power supply1.8 V
Certification statusNot Qualified
Maximum slew rate117 mA
Nominal supply voltage1.8 V
surface mountYES
Terminal surfaceMatte Tin (Sn)
Si550
R
EVISION
D
V
O L TA G E
- C
O N T R O L L E D
C
R Y S TA L
O
S C I L L A T O R
(VCXO)
10 MH
Z T O
1.4 G H
Z
Features
Available with any-rate output
frequencies from 10 to 945 MHz
and selected frequencies to
1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
Si5602
Ordering Information:
See page 8.
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 7.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory-configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating the long lead times associated with custom oscillators.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
®
Clock Synthesis
ADC
Vc
OE
GND
Rev. 0.6 6/07
Copyright © 2007 by Silicon Laboratories
Si550
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