P4C1024L
LOW POWER
128K x 8 CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
– Operating: 70mA/85mA
– CMOS Standby: 150µA/150µA
Access Times
– 55/70/100 ns (Commercial or Industrial)
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
1
, CE
2
, and
OE
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
– 32-Pin 600 mil Plastic and Ceramic DIP
– 32-Pin 445 mil SOP
– 32-Pin TSOP
– 32-Pin LCC (400x820 mil) [Two-Sided]
DESCRIPTIOn
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 55 ns, 70 ns, and 100 ns are available.
CMOS is utilized to reduce power consumption to a low
level.
The P4C1024L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
16
. Reading is ac-
complished by device selection (CE
1
low and CE
2
high)
and output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions,
the data in the addressed memory location is presented
on the data input/output pins. The input/output pins stay
in the HIGH Z state when either CE
1
or
OE
is HIGH or
WE
or
CE
2
is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, 600 mil PDIP, or 32-pin LCC package.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP(P600, C10), SOP (S12), LCC (L1)
TOP VIEW
TSOP configuration at end of datasheet
Document #
SRAM125
REV H
Revised May 2011
P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
I
OUT
I
LAT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Output Current into Low
Outputs
Latch-up Current
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-55 to +125
-55 to +125
-65 to +150
Unit
V
V
°C
°C
°C
mA
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Max
7
9
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
I
OH
=-1mA, V
CC
=4.5V
I
OL
=2.1mA
2.2
-0.5
MIL
Input Leakage Current
GND ≤ V
IN
≤ V
CC
IND
COM
MIL
I
LO
Output Leakage Current
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
GND ≤ V
OUT
≤ V
CC
,
CE
1
≥ V
IH
or CE
2
≤ V
IL
V
CC
=5.5V, I
OUT
=0mA
CE
1
=V
IH
or CE
2
=V
IL
V
CC
=5.5V, I
OUT
=0mA
CE
1
≥ V
CC
-0.2V, CE
2
≤ 0.2V
IND
COM
-10
-5
-2
-10
-5
-2
Min
2.4
0.4
V
CC
+ 0.3
0.8
+10
+5
+2
+10
+5
+2
3
mA
µA
µA
Max
Unit
V
V
V
V
I
SB
I
SB1
50
µA
Document #
SRAM125
REV H
Page 2
P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM
POWER DISSIPATIOn CHARACTERISTICS
Sym
I
CC
Parameter
Dynamic Operating Current
Temperature Range
Commercial
Industrial/Military
*
-55
70
85
-70
70
85
-100
70
85
-55
15
25
**
-70
15
25
-100
15
25
Unit
mA
mA
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥ V
IH
(min),
CE
1
and
WE
≤ V
IL
(max),
OE
is high. Switching inputs are 0V
and 3V.
** As above but @ f=1 MHz and V
IL
/ V
IH
= 0V/V
CC
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down
0
55
5
20
0
70
5
10
20
30
5
25
0
100
-55
Min
55
55
55
5
10
25
35
5
30
Max
Min
70
70
70
5
10
30
40
-70
Max
Min
100
100
100
-100
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(1)
Document #
SRAM125
REV H
Page 3
P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM
TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE COnTROLLED)
notes:
1. WE is HIGH for READ cycle.
2.
CE
1
and
OE
are LOW, and CE
2
is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transi-
tion LOW or CE
2
transition HIGH.
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM125
REV H
Page 4
P4C1024L - LOW POWER 128K x 8 CMOS STATIC RAM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
5
-55
Min
55
50
50
0
40
0
25
0
25
5
Max
Min
70
60
60
0
50
0
30
0
30
5
-70
Max
Min
100
75
75
0
60
0
35
0
35
-100
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(6)
Notes:
6.
CE
1
and
WE
are LOW and CE
2
is HIGH for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
8. If
CE1
goes HIGH or CE2 goes LOW simultaneously with
WE
HIGH,
the output remains in a high impedance state
9.
Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM125
REV H
Page 5
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