Philips Semiconductors
Product specification
I
2
C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
FEATURES
•
Dual Noise Reduction (NR) channels
•
Head preamplifiers
•
Reverse head switching
•
Automatic Music Search (AMS)
•
Blank skip
•
Mute position
•
Equalization with electronically switched time constants
•
Switch functions and level adjustment controlled via
I
2
C-bus
•
Optional switch inputs TTL compatible
•
Dolby reference level = 387.5 mV
•
Contained in a 32-pin small outline package
•
Improved EMC behaviour.
GENERAL DESCRIPTION
The TEA0679T is a bipolar integrated circuit that provides
two channels of Dolby B noise reduction for playback
applications in car radios. It includes head and
equalization amplifiers with electronically switchable time
constants. The device also includes electronically
switchable inputs for tape drivers with reverse heads.
This device detects pauses of music in the Automatic
Music Search (AMS) scan mode (for applications with an
intelligent controlled tape driver) or AMS latch mode (for
applications with a simple controlled tape driver).
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
S
+
N
-------------
-
N
supply voltage
supply current
signal plus noise-to-noise ratio
PARAMETER
−
78
MIN.
7.6
−
35
84
TYP.
TEA0679T
For both modes the delay time can be fixed by using an
external resistor. In the blank skip mode the IC can detect
pauses of music during playback and allows a
microcontroller to react on this situation.
The equalization amplifier gain adjustment, the output
offset adjustment and all switching functions are I
2
C-bus
controlled. Head switching and equalization time constant
switching can be controlled via separate pins (optional).
The device operates with power supplies from 7.6 to 12 V.
The output overload level increases with increases in
supply voltage.
Current drain varies with the following variables:
•
Supply voltage
•
Noise reduction on/off
•
AMS on/off.
Because of this current drain variation it is advisable to use
a regulated power supply or a supply with a long time
constant.
MAX.
12
40
−
UNIT
V
mA
dB
ORDERING INFORMATION
TYPE
NUMBER
TEA0679T
PACKAGE
NAME
SO32
DESCRIPTION
plastic small outline package; 32 leads; body width 7.5 mm
VERSION
SOT287-1
Remark Dolby*:
Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111,
USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby
Laboratories Licensing Corporation.
1998 Nov 12
2
Philips Semiconductors
Product specification
I
2
C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
PINNING
SYMBOL
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
V
CC
INA1
V
ref
INA2
INB2
HS
INB1
AGND
EQFB
EQB
SCB
HPB
CONTRB
INTB
OUTB
AMS
DGND
SCL
SDA
BEN
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DESCRIPTION
programmable address bit
blank skip reference capacitance
delay time constant
blank skip integration capacitance
equalization switch input (optional)
output channel A
integrating filter channel A
control voltage channel A
high-pass filter channel A
side chain channel A
equalizing output channel A
equalizing input channel A
supply voltage
input channel A1 (forward or reverse)
reference voltage
input channel A2 (reverse or forward)
input channel B2 (reverse or forward)
head switch input (optional)
input channel B1 (forward or reverse)
analog ground
equalizing input channel B
equalizing output channel B
side chain channel B
high-pass filter channel B
control voltage channel B
integrating filter channel B
output channel B
Automatic Music Search (AMS)
output
digital ground
serial clock input
serial data input/output
bus enable
HPA 9
SCA 10
EQA 11
EQFA 12
VCC 13
INA1 14
Vref 15
INA2 16
MHB118
TEA0679T
handbook, halfpage
MAD 1
BSC 2
TD 3
BTC 4
EQS 5
OUTA 6
INTA 7
CONTRA 8
32 BEN
31 SDA
30 SCL
29 DGND
28 AMS
27 OUTB
26 INTB
25 CONTRB
TEA0679T
24 HPB
23 SCB
22 EQB
21 EQFB
20 AGND
19 INB1
18 HS
17 INB2
Fig.2 Pin configuration.
1998 Nov 12
4
Philips Semiconductors
Product specification
I
2
C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
FUNCTIONAL DESCRIPTION
The following functions can be controlled via the I
2
C-bus:
•
Equalization time constant switching
•
Head switching
•
Automatic Music Search (AMS) modes and blank skip
•
Noise Reduction (NR) on/off switching
•
Mute switching
•
Equalization amplifier gain adjustment
•
Output offset adjustment.
Dolby B noise reduction only operates correctly if the 0 dB
Dolby level is adjusted at 387.5 mV. The gain adjustment
can also be used to change the AMS level detector
threshold. The IC is able to generate an internal power-on
reset to guarantee a proper start-up behaviour.
Two of the above functions can be controlled via separate
pins (optional), if required.
Head switching is achieved when pin HS is connected to a
LOW level (input IN2 active) or connected to a HIGH level
(input IN1 active).
Equalization time constant switching (70 or 120
µs)
is
achieved when pin EQS is connected to a LOW level
(70
µs)
or connected to a HIGH level (120
µs).
If I
2
C-bus control is used the respective external function
control pin has to be left open-circuit. When open-circuit
the current state of the function can be observed at these
pins.
Automatic Music Search (AMS) modes and blank skip
If AMS is active (search mode bits SMOD1 = 1 and
SMOD0 = 0 or 1) the NR function is internally switched off
and the equalization time constant is internally forced to
70
µs.
The signals of both channels are full-wave rectified
and then added. This means that even if one channel
appears inverted to the other channel the normal AMS
function is ensured.
It is possible to choose between the AMS scan and the
AMS latch mode via the I
2
C-bus. Due to the usage of an
internal flip-flop the switching from one mode to the other
must be done via the AMS off state. This guarantees an
appropriate flip-flop reset:
•
Start from the initial AMS off state (SMOD1 = 0 and
SMOD0 = 0 or 1)
•
Enable the desired AMS operation mode: AMS latch
mode (SMOD1 = 1 and SMOD0 = 0) or AMS scan mode
(SMOD1 = 1 and SMOD0 = 1).
TEA0679T
For further information on music search see Figs 4 to 8.
If blank skip is active (SMOD1 = 0 and SMOD0 = 1)
periods of music can be detected in the playback mode
using the AMS pin as the detector output. It is possible to
defeat this function via the I
2
C-bus (SMOD1 = 0 and
SMOD0 = 0). For further information on blank skip
see Figs 9 and 10.
Offset adjustment procedure
The offset adjustment is performed using two bits in the
I
2
C-bus write byte 0. The offset monitor bit OMOR enables
the AMS output to indicate whether the selected offset
value is positive or negative. The channel select bit OFCH
selects the channel (A or B) which is currently monitored
by the output at pin AMS. The monitoring needs a few
microseconds until the output result is valid. A complete
offset adjustment is performed in the following way:
•
Adjust the output to Dolby level using the I
2
C-bus
controlled equalization gain adjustment
•
Enable the offset monitor and select the channel to be
monitored by transmitting the bits OMOR = 1 and OFCH
(0 = Channel A, 1 = Channel B) to the IC
•
If the monitor output (pin AMS) is LOW send the next
offset value OFFCHA or OFFCHB one offset step below
the last valid value. If the monitor output (pin AMS) is
HIGH send the next offset value OFFCHA or OFFCHB
one offset step above the last valid value
•
Repeat the last two steps until the monitor output
changes its polarity
•
If necessary store the transmitted digital offset value for
the selected channel.
The start value is either set by the power-on reset or the
last I
2
C-bus transmission. The offset adjustment can be
performed during the power-on reset condition and also
each time the tape driver is not active. A complete digital
offset data set consists of four values: one for each head
(head 1 and head 2) in each channel. After an offset value
transmission the IC stores one value for channel A and
one value for channel B. If a head switch is performed
these values have to be updated via the I
2
C-bus for the
alternative head.
1998 Nov 12
5
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