without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/26/07
1
IS24C02A
IS24C04A
IS24C08A
IS24C16A
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
SDA
5
WP
7
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
X
DECODER
SCL
6
CONTROL
LOGIC
EEPROM
ARRAY
Y
DECODER
GND
4
nMOS
ACK
Clock
DI/O
>
DATA
REGISTER
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/26/07
IS24C02A
IS24C04A
IS24C08A
IS24C16A
PIN CONFIGURATION
8-pad DFN
PIN CONFIGURATION
8-Pin DIP, SOIC, DFN, TSSOP, MSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
The IS24C04A uses A1 and A2 pins for hardwire addressing
and a total of four devices may be addressed on a single bus
system. The A0 pin is a no connect in the IS24C04A. When
the A1 or A2 input is left floating, the input internally defaults
to zero.
The IS24C08A only uses the A2 input for hardwire addressing
and a total of two devices may be addressed on a single bus
system. The A0 and A1 pins are no connects in the
IS24C08A. When the A2 input is left floating, the input
internally defaults to zero.
These pins are not used by IS24C16A . The A0, A1, and A2 pins
are no connects in the IS24C16A.
WP
WP is the Write Protect pin. If the WP pin is tied to V
CC
on
the IS24C02A, IS24C04A, IS24C08A and IS24C016A, the
entire array becomes Write Protected (Read only). When WP
is tied to GND or left floating normal read/write operations are
allowed to the device.
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data
into and out of the device. The SDA pin is an open drain output and
can be wire-Or'ed with other open drain or open collector
outputs. The SDA bus
requires
a pullup resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C02A uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/26/07
3
IS24C02A
IS24C04A
IS24C08A
IS24C16A
The EEPROM monitors the SDA and SCL lines and will
not respond until the Start condition is met.
DEVICE OPERATION
IS24C02A/04A/08A/16A features serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I
2
C
TM
.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C02A/04A/08A/16A is the Slave device on the bus.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The
IS24C02A/04A/08A/16A
contains a reset function
in case the 2-wire bus transmission is accidentally
interrupted (eg. a power loss), or needs to be
terminated mid-stream. The reset is caused when the
Master device creates a Start condition. To do this, it
may be necessary for the Master device to monitor the
SDA line while cycling the SCL up to nine times. (For
each clock signal transition to High, the Master checks
for a High level on SDA.)
The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a Start
or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of the
High period of the clock signal. The data on the SDA line may
be changed during the Low period of the clock signal. There
is one clock pulse per bit of data. Each data transfer is
initiated with a Start condition and terminated with a Stop
condition.
Standby Mode
Power consumption is reduced in standby mode. The
IS24C02A/04A/08A/16A will enter standby mode: a) At
Power-up, and remain in it until SCL or SDA toggles; b)
Following the Stop signal if a no write operation is
initiated; or c) Following any internal write operation.
Start Condition
The Start condition precedes all commands to the device and
is defined as a High to Low transition of SDA when SCL is High.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/26/07
IS24C02A
IS24C04A
IS24C08A
IS24C16A
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C02A/04A/08A/
16A. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C02A/04A/08A/16A
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave address are fixed
as 1010 for the IS2402A/04A/08A/16A.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C02A uses the three bits A0, A1, and A2 in a
comparison with the hard-wired input values on the A0, A1,
and A2 pins. Up to eight IS24C02A units may share the 2-
wire bus.
The IS24C04A uses the bit B0 to address either the upper
or the lower 256 byte block in the device. Also, the bits A1
and A2 are used in a comparison with the hard-wired input
values on the A1 and A2 pins. Up to four IS24C04A units
may share the 2-wire bus.
The IS24C08A uses the bits B0 and B1 to address one of
the four 256 byte blocks in the device. Also, the bit A2 is
used in a comparison with the hard-wired input value on the
A2 pin. Up to two IS24C08A units may share the 2-wire
bus.
The IS24C16A uses the bits B0, B1, and B2 to address one
of the eight 256 byte blocks in the device.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02A/04A/08A/16A) will respond with ACK on the
SDA line. The Slave will pull down the SDA on the ninth
clock cycle, signaling that it received the eight bits of data.
The selected EEPROM then prepares for a Read or Write
operation by monitoring the bus.
Page Write
The IS24C02A/04A/08A/16A is capable of 16-byte Page-
Write operation. A Page-Write is initiated in the same manner
as a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 15 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the four lower order data word address
bits are internally incremented by one, while the higher order
bits of the data word address remain constant. If a byte
address is incremented from the last byte of a page, it
returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the Stop
condition, the address counter will “roll over,” and the previously
written data will be overwritten. Once all 16 bytes are
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all
received data is written to the IS24C02A/04A/08A/16A in a
single Write cycle. All inputs are disabled until completion of
the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C02A/04A/08A/16A initiates the internal Write cycle.
ACK polling can be initiated immediately. This involves
issuing the Start condition followed by the Slave address for
a Write operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C02A/04A/
08A/16A has completed the Write operation, an ACK will be
returned and the host can then proceed with the next Read
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