Processor Specific Clock Generator, 200MHz, CMOS, PDSO48, SSOP-48
CY28159PVC Parametric
Parameter Name
Attribute value
Maker
Silicon Laboratories Inc
Parts packaging code
SSOP
package instruction
SSOP,
Contacts
48
Reach Compliance Code
unknown
ECCN code
EAR99
JESD-30 code
R-PDSO-G48
JESD-609 code
e0
length
15.875 mm
Humidity sensitivity level
1
Number of terminals
48
Maximum operating temperature
70 °C
Minimum operating temperature
Maximum output clock frequency
200 MHz
Package body material
PLASTIC/EPOXY
encapsulated code
SSOP
Package shape
RECTANGULAR
Package form
SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)
220
Master clock/crystal nominal frequency
14.31818 MHz
Certification status
Not Qualified
Maximum seat height
2.794 mm
Maximum supply voltage
3.465 V
Minimum supply voltage
3.135 V
Nominal supply voltage
3.3 V
surface mount
YES
technology
CMOS
Temperature level
COMMERCIAL
Terminal surface
TIN LEAD
Terminal form
GULL WING
Terminal pitch
0.635 mm
Terminal location
DUAL
Maximum time at peak reflow temperature
NOT SPECIFIED
width
7.5 mm
uPs/uCs/peripheral integrated circuit type
CLOCK GENERATOR, PROCESSOR SPECIFIC
CY28159PVC Preview
CY28159
Clock Generator for Serverworks Grand Champion Chipset
Applications
1CY28159
Features
• Eight differential CPU clock outputs
• One PCI output
• One 14.31818 MHz reference clock
• Two 48 MHz clocks
Table 1. Frequency Selection
SEL 100/133
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
S1
0
1
0
1
0
1
0
1
CPU(0:7), CPU#(0:7)
100 MHz
100 MHz
100 MHz
Hi-Z
133.3MHz
133.3MHz
200MHz
N/A
3V33
33.3MHz
33.3MHz
Disable
Hi-Z
33.3MHz
33.3MHz
33.3MHz
N/A
48M(0,1)
48 MHz
Disable
Disable
Hi-Z
48 MHz
Disable
48 MHz
N/A
Notes
Normal Operation
Test Mode(recommended)
Test Mode (optional)
Hi-Z all outputs
Optional
Optional
o7ptional
Reserved
• All outputs compliant with Intel
®
specifications
• External resistor for current reference
• Selection logic for differential swing control, test mode,
Hi-Z, power-down and spread spectrum
• 48-pin SSOP and TSSOP packages
Table 2.
Block Diagram
Pin Configuration
3V33
VDD
48M0/S0
48M1/S1
VSS
VDD
CPU0
CPU0#
VSS
CPU1
CPU1#
VDD
CPU2
CPU2#
VSS
CPU3
CPU3#
VDD
REF
SSCG#
VSS
XIN
XOUT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
VSS
VDDA
VSSA
PD#
VDD
CPU4
CPU4#
VSS
CPU5
CPU5#
VDD
CPU6
CPU6#
VSS
CPU7
CPU7#
VDD
MULT0
MULT1
VSS
VSSA
IREF
VDDA
XIN
XOUT
MultSel(0:1)
I_Ref
OSC
VDDI
I
Control
REF
CPU (0:7)
CPU (0:7)#
SSCG#
SEL100/133
VCO
48M(0,1)/S(0,1)
PD#
S(0,1)
VDDL
3V33
VSSL
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
CY28159
VSSI
Page 1 of 12
www.SpectraLinear.com
CY28159
Pin Description
Pin
20
Name
SSCG
I/O
[1]
PU
I
O
Description
When asserted LOW, this pin invokes Spread Spectrum functionality. Spread
spectrum is applicable to CPU(0:7), CPU(0:7)#. This pin has a 250-k internal
pull-up.
Differential host clock outputs. These outputs are used in pairs, (CPU0-0#,
CPU1-1#, CPU2-2#, CPU3-3#, CPU4-4#, CPU5-5#, CPU6-6#, and CPU7-7#)
for differential clocking of the host bus. CPU(0:7) are 180 degrees out of phase
with their complements, CPU(0:7)#. See
Table 1
on page 1
This pin establishes the reference current for the internal current steering
buffers of the CPU clocks. A resistor is connected from this pin to ground to set
the value of this current.
Fixed 33.3-MHz clock output.
When asserted LOW, this pin invokes a power-down mode by shutting off all
the clocks, disabling all internal circuitry, and shutting down the crystal oscil-
lator. The 48M(0:1) and REF clocks are driven LOW during this condition and
the CPU clocks are driven HIGH and programmed with an 2X IREF current. It
has a 250-k internal pull-up.
S0 and S1 inputs are sensed on power-up and then internally latched. After-
wards the pins are 3V 48-MHz clocks.
Input select pin. See
Table 1
on page 1.
It has a 250-k internal Pull-up
Crystal Buffer output pin. Connects to a crystal only. When an external signal
other than a crystal is used or when in Test mode, this pin is kept unconnected.
Crystal Buffer input pin. Connects to a crystal, or an external single ended input
clock signal.
A buffered output clock of the signal applied at Xin. Typically, 14.31818 MHz.
These input select pins configure the Ioh current (and thus the Voh swing
amplitude) of the CPU clock output pairs. Each pin has a 250-k internal
Pull-up.
See Table 6
for current and resistor values.
3.3V power supply pins.
3.3V power supply pins for common supply to the core.
Ground pins for common supply to the core.
Ground pins.
7,10, 13, 16,
42, 39, 36, 33
8, 11, 14, 17,
41, 38, 35, 32
26
CPU(0:7)
CPU(0:7)#
IRef
P
1
44
3V33
PD#
O
PU
I
3, 4
48
23
22
19
30, 29
48M(0,1), S(0,1)
SEL100/133
XOUT
XIN
REF
Mult(0,1)
IO
PU
I
O
I
O
I
25, 46
2, 6, 12, 18, 24,
31, 37, 43
5, 9, 15, 21, 28,
34, 40, 47
27, 45
VDDA
VDD
VSS
VSSA
P
P
P
P
Note:
1. Definition of I/O column mnemonic on pin description table above 1= Input pin, O = output pin, P = power supply pin, PU = indicates that a bidirectional pin contains
pull-up resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD designation are guaranteed
to be seen as a logic 0 level if no external level setting circuitry is present at power up.
Rev 1.0, November 24, 2006
Page 2 of 12
CY28159
Table 3. Group Offset Specifications
Group
CPU to 3V33
CPU to REF
Offset
No requirement
No requirement
Comments
Table 4. Group Limits and Parameters (Applicable to all
settings: Sel133/100#=x)
Output Name
CPU[(0:7)#]
REF
3V33
Max Load
See
Figure 1
20 pF
30 pF
Test Load Configuration
The following shows test load configurations for the different Host Clock Outputs.(MULTsel1 = 0, MULTsel0 =1
T
PCB
VDD
CPUT
2pF
Measurement Point
MULTSEL
T
PCB
CPUT#
2pF
Measurement Point
Figure 1. 0.7V Test Load Termination
Output Under Test
Probe
C
LOAD
Figure 2. Lumped Load Termination
Rev 1.0, November 24, 2006
Page 3 of 12
CY28159
3.3V signals
tD C
-
-
3.3V
2.4V
1.5V
0.4V
0V
Tr
Tf
Figure 3. 3.3V Measurement Points
Rev 1.0, November 24, 2006
Page 4 of 12
CY28159
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for
maximum efficiency in minimizing Electro-Magnetic Inter-
Table 5. Spectrum Spreading Selection Table
Unspread Frequency in MHz
F Min(MHz)
100
133.3
200
99.5
132.66
199.5
Spread Spectrum Parameter
Downspreading
F Center(MHz)
99.75
132.67
199.75
F Max(MHz)
100
133
200
Spread (%)
–0.5%
–0.5%
–0.5%
ference radiation generated from repetitive digital signals
mainly clocks. For a detailed explanation of Spread Spectrum
Clock Generation.
Power Management Functions
Table 6. Host Swing Select Functions
[2]
Multsel0
0
0
0
0
1
1
1
1
MultSel1
0
0
1
1
0
0
1
1
Board Target
Trace/TermZ
60 Ohms
50 Ohms
60 Ohms
50 Ohms
60 Ohms
50 Ohms
60 Ohms
50 Ohms
Reference Rr, Iref = Vdd(3*Rr)
Note 3
Rf = 475 1%,
Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Rr = 475 1%,Iref = 2.32 mA
Output Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh@Z, Iref = 2.32
mA
07V@60
0.59V @ 50
0.85V @ 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
Notes:
2. The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.
3. Rr refers to the resistance placed in series with the Iref input and V
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