Freescale Semiconductor
Technical Data
Document Number: MPC8260EC
Rev. 1.3, 10/2005
MPC8260
PowerQUICC™ II Integrated
Communications Processor
Hardware Specifications
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the .29
µm
(HiP3) devices of the
PowerQUICC II™ family of communications processors:
the MPC8260 and the MPC8255. Throughout this
document, the MPC8260 and the MPC8255 are collectively
referred to as the MPC8260.
1.
2.
3.
4.
5.
6.
7.
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical and Thermal Characteristics . . . . . . . . . . . . 5
Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 19
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 37
Document Revision History . . . . . . . . . . . . . . . . . . . 38
© Freescale Semiconductor, Inc., 2003, 2005. All rights reserved.
Features
NOTE: Document Revision History
Changes to this document are summarized in
Table 17.
Figure 1
shows the block diagram for the MPC8260.
16 Kbytes
I-Cache
I-MMU
G2 Core
System Interface Unit
(SIU)
16 Kbytes
D-Cache
D-MMU
Bus Interface Unit
60x-to-Local
Bridge
Memory Controller
Communication Processor Module (CPM)
Clock Counter
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
2 Virtual
IDMAs
Interrupt
Controller
24 Kbytes
Dual-Port RAM
Serial
DMAs
System Functions
60x Bus
Local Bus
32 bits, up to 66 MHz
MCC1
1
MCC2
FCC1
FCC2
FCC3
1
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Time Slot Assigner
Serial Interface
8 TDM Ports
2
3 MII
Ports
3
2 UTOPIA
Ports
Non-Multiplexed
I/O
Notes:
1
Not on MPC8255
2
4 on the MPC8255
3
2 on the MPC8255
Figure 1. MPC8260 Block Diagram
1
Features
The major features of the MPC8260 are as follows:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the
MPC8255)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
2
Freescale Semiconductor
Features
•
•
•
•
•
•
•
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
3
Features
•
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
— Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers (two on the MPC8255) supporting the following
protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
2
C) controller (identical to the MPC860 I
2
C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
4
Freescale Semiconductor
Electrical and Thermal Characteristics
— Up to eight TDM interfaces (4 on the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
2
2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8260.
This section describes the DC electrical characteristics for the MPC8260.
Table 1
shows the maximum
electrical ratings.
Table 1. Absolute Maximum Ratings
1
Rating
Core supply voltage
2
PLL supply voltage
2
I/O supply voltage
3
Input voltage
4
Junction temperature
Storage temperature range
1
Symbol
VDD
VCCSYN
VDDH
VIN
T
j
T
STG
Value
-0.3 – 2.75
-0.3 – 2.75
-0.3 – 4.0
GND(-0.3) – 3.6
120
(-55) – (+150)
Unit
V
V
V
V
°C
°C
Absolute maximum ratings are stress ratings only; functional operation (see
Table 2)
at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2
Caution:
VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.
3
Caution:
VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.0 V during normal operation.
4
Caution:
VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
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