CY2304
3.3V Zero Delay Buffer
Features
■
■
■
■
■
■
■
■
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations
Multiple low-skew outputs
10 MHz to 133 MHz operating range
90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
Space-saving 8-pin 150-mil SOIC package
3.3V operation
Industrial temperature available
required to be driven into the FBK pin, and can be obtained from
one of the outputs. The input-to-output skew is guaranteed to be
less than 250 ps, and output-to-output skew is guaranteed to be
less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25
μA
of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in
Table 1
on page 1. The CY2304–1 is the base part,
where the output frequencies equal the reference if there is no
counter in the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the feedback
pin.
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip phase-locked loop (PLL) that locks to an
input clock presented on the REF pin. The PLL feedback is
Logic Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Table 1. Available Configurations
Device
CY2304-1
CY2304-2
CY2304-2
FBK from
Bank A or B
Bank A
Bank B
Bank A Frequency
Reference
Reference
2 × Reference
Bank B Frequency
Reference
Reference/2
Reference
Pinouts
Figure 1. 8-Pin SOIC - Top View
REF
CLKA1
CLKA2
GND
1
2
3
4
8
7
6
5
FBK
V
DD
CLKB2
CLKB1
Cypress Semiconductor Corporation
Document #: 38-07247 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 12, 2009
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CY2304
l
Table 2. Pin Definitions - 8-Pin SOIC
Pin
1
2
3
4
5
6
7
8
Signal
REF
[1]
CLKA1
[2]
CLKA2
[2]
GND
CLKB1
[2]
CLKB2
[2]
V
DD
FBK
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3V supply
PLL feedback input
Description
Input reference frequency, 5V tolerant input
Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving
the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown in
Figure 2.
For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If
input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and
remaining outputs.
For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note
AN1234
“CY2308: Zero Delay Buffer.”
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Document #: 38-07247 Rev. *F
Page 2 of 9
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CY2304
Maximum Ratings
Supply Voltage to Ground Potential.................–0.5V to +7.0V
DC Input Voltage (Except Ref) ...............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF.............................................–0.5 to 7V
Storage Temperature ..................................–65°C to +150°C
Junction Temperature ..................................................150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................> 2000V
Operating Conditions for CY2304SC-X Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance (below 100 MHz)
Load Capacitance (from 100 MHz to 133 MHz)
Input Capacitance
[3]
Power up time for all V
DD
s to reach minimum specified voltage (power
ramps must be monotonic)
Description
Min
3.0
0
–
–
–
0.05
Max
3.6
70
30
15
7
50
Unit
V
°C
pF
pF
pF
ms
Electrical Characteristics for CY2304SC-X Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
[4]
Output HIGH Voltage
[4]
Supply Current
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA (–1, –2)
I
OH
= –8 mA (–1, –2)
Unloaded outputs, 100 MHz REF, Select
inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF (–1,–2)
Unloaded outputs, 33 MHz REF (–1,–2)
Test Conditions
Min
–
2.0
–
–
–
2.4
–
–
–
–
Max
0.8
–
50.0
100.0
0.4
–
12.0
45.0
32.0
18.0
Unit
V
V
μA
μA
V
V
μA
mA
mA
mA
I
DD
(PD mode) Power Down Supply Current REF = 0 MHz
Switching Characteristics for CY2304SC-X Commercial Temperature Devices
Parameter
[5]
t
1
t
1
t
DC
t
DC
t
3
t
3
Name
Output Frequency
Output Frequency
Duty Cycle
[4]
= t
2
÷
t
1
(–1,–2)
Duty Cycle
[4]
= t
2
÷
t
1
(–1,–2)
Rise Time
[4]
(–1, –2)
Rise Time
[4]
(–1, –2)
Test Conditions
30 pF load, all devices
15 pF load, –1, –2 devices
Measured at 1.4V,
F
OUT
= 66.66 MHz, 30 pF load
Measured at 1.4V,
F
OUT
< 50 MHz, 15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Min
10
10
40.0
45.0
–
–
Typ.
–
–
50.0
50.0
–
–
Max
100
133.3
60.0
55.0
2.20
1.50
Unit
MHz
MHz
%
%
ns
ns
Notes
3. Applies to both REF clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded output.
Document #: 38-07247 Rev. *F
Page 3 of 9
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CY2304
Switching Characteristics for CY2304SC-X Commercial Temperature Devices
(continued)
Parameter
[5]
t
4
t
4
t
5
Name
Fall Time
[4]
(–1, –2)
Fall Time
[4]
(–1, –2)
Output-to-Output Skew on
same Bank (–1,–2)
[4]
Output Bank A to Output
Bank B Skew (–1)
Output Bank A to Output
Bank B Skew (–2)
t
6
t
7
t
J
Skew, REF Rising Edge to
FBK Rising Edge
[4]
Device-to-Device Skew
[4]
Cycle-to-Cycle Jitter
[4]
(–1)
Test Conditions
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
devices
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
t
J
Cycle-to-Cycle Jitter
[4]
(–2)
Measured at 66.67 MHz, loaded outputs 30
pF load
Measured at 66.67 MHz, loaded outputs 15
pF load
t
LOCK
PLL Lock Time
[4]
Stable power supply, valid clocks
presented on REF and FBK pins
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
0
0
90
–
–
–
–
–
Max
2.20
1.50
200
200
400
±250
500
175
200
100
400
375
1.0
Unit
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
Operating Conditions for CY2304SI-X Industrial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance (below 100 MHz)
Load Capacitance (from 100 MHz to 133 MHz)
Input Capacitance
Description
Min
3.0
–40
–
–
–
Max
3.6
85
30
15
7
Unit
V
°C
pF
pF
pF
Electrical Characteristics for CY2304SI-X Industrial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
[4]
Output HIGH Voltage
[4]
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA (–1, –2)
I
OH
= –8 mA (–1, –2)
Test Conditions
Min
–
2.0
–
–
–
2.4
Max
0.8
–
50.0
100.0
0.4
–
Unit
V
V
μA
μA
V
V
Document #: 38-07247 Rev. *F
Page 4 of 9
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CY2304
Electrical Characteristics for CY2304SI-X Industrial Temperature Devices
(continued)
Parameter
I
DD
Description
Supply Current
Test Conditions
Unloaded outputs, 100 MHz, Select inputs
at V
DD
or GND
Unloaded outputs, 66 MHz REF (–1, –2)
Unloaded outputs, 33 MHz REF (–1, –2)
Min
–
–
–
–
Max
25.0
45.0
35.0
20.0
Unit
μA
mA
mA
mA
I
DD
(PD mode) Power Down Supply Current REF = 0 MHz
Switching Characteristics for CY2304SI-X Industrial Temperature Devices
Parameter
[5]
t
1
t
1
t
DC
t
DC
t
3
t
3
t
4
t
4
t
5
Name
Output Frequency
Output Frequency
Duty Cycle
[4]
= t
2
÷
t
1
(–1,–2)
Duty Cycle
[4]
= t
2
÷
t
1
(–1,–2)
Rise Time
[4]
(–1, –2)
Rise Time
[4]
(–1, –2)
Fall Time
[4]
(–1, –2)
Fall Time
[4]
(–1, –2)
Output-to-Output Skew on
same Bank (–1,–2)
[4]
Output Bank A to Output
Bank B Skew (–1)
Output Bank A to Output
Bank B Skew (–2)
t
6
t
7
t
J
Skew, REF Rising Edge to
FBK Rising Edge
[4]
Device-to-Device Skew
[4]
Cycle-to-Cycle Jitter
[4]
(–1)
Test Conditions
30 pF load, All devices
15 pF load, All devices
Measured at 1.4V, F
OUT
= 66.66 MHz,
30 pF load
Measured at 1.4V, F
OUT
< 50 MHz,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
devices
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
t
J
Cycle-to-Cycle Jitter
[4]
(–2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
t
LOCK
PLL Lock Time
[4]
Stable power supply, valid clocks
presented on REF and FBK pins
Min
10
10
40.0
45.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50.0
50.0
–
–
–
–
–
–
–
0
0
–
–
–
–
–
–
Typ.
Max
100
133.3
60.0
55.0
2.50
1.50
2.50
1.50
200
200
400
±250
500
180
200
100
400
380
1.0
Unit
MHz
MHz
%
%
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
Document #: 38-07247 Rev. *F
Page 5 of 9
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