EEWORLDEEWORLDEEWORLD

Part Number

Search

UPD63335GA-9EU

Description
Consumer Circuit, MOS, PQFP48, 7 X 7 MM, FINE PITCH, PLASTIC, TQFP-48
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size451KB,56 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD63335GA-9EU Overview

Consumer Circuit, MOS, PQFP48, 7 X 7 MM, FINE PITCH, PLASTIC, TQFP-48

UPD63335GA-9EU Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeQFP
package instructionLFQFP,
Contacts48
Reach Compliance Codecompliant
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeS-PQFP-G48
JESD-609 codee0
length7 mm
Number of functions1
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.27 mm
Maximum slew rate65 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
surface mountYES
technologyMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm

UPD63335GA-9EU Preview

DATA SHEET
MOS INTEGRATED CIRCUITS
µ
PD63335
STEREO SOUND CODEC
DESCRIPTION
The
µ
PD63335 is a stereo sound codec LSI that enables full-duplex communications and features two channels
each of on-chip 16-bit ADC and DAC circuits for mutual conversion between digital signals and audio analog signals
(having a maximum signal bandwidth of 20 kHz).
The analog signal input block enables four pairs of stereo signals plus three monaural signals to be output from
the output stage's internal mixing circuit, which can then be multiplexed and input to the ADC. One type of monaural
signal can be selected from two external pins via a selector as a monaural signal connected to an internal
microphone amplifier (MIC amp), with selectable gain of 0 dB or 20 dB.
The analog signal output block enables mixed output of analog signals output by the DAC, four pairs of stereo
analog signals, and an output signal from the MIC amp, and the volume of each signal can be controlled
independently before mixing. The digital audio signal I/O block supports an audio-type serial interface (two's
complement). In addition, a clocked serial interface (CSI) can be used for direct connection to a general-purpose
microcontroller for access to internal registers such as for volume control.
FEATURES
Two channels each of over sample
Σ
type ADC and DAC
• ADC SNR = 85 dB Typ.
• DAC SNR = 90 dB Typ.
ADC and DAC digital filter characteristics
• Pass band ripple:
±0.1
dB (0 to 0.4 f
S
) for ADC and DAC
• Stop band attenuation:
−74
dB (0.6 f
S
) or above for ADC and DAC
0.4 to 48 kHz
Sampling frequency (f
S
):
• Division rate from master clock can be set to 3072, 1536, 768, or 512
Analog input block includes a multiplexer and analog output block includes a mixing circuit
Low-noise monaural MIC amp is on chip
On-chip reference voltage power supply (1.4 V (TYP.))
Low supply voltage operation:
DV
DD
= 3.3 V, AV
DD
= 3.3 V
Support for power down mode in each internal block
Operating ambient temperature:
−40
to +85°C
APPLICATIONS
• Speech recognition systems, including car navigation systems
• Electronic toys with speech/audio I/O functions
ORDERING INFORMATION
Part Number
Package
48-pin plastic TQFP (fine pitch) (7 × 7)
µ
PD63335GA-9EU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15003EJ6V0DS00 (6th edition)
Date Published February 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µ
PD63335
BLOCK DIAGRAM
Digital data interface
BIT_CLK
LRCLK
Digital command interface
XTL_OUT
MSWDT
MSRDT
MSCLK
XTL_IN
RESET
SO
SI
I/O Interface
Digital Filter
Decimator
Decimator
Loop-back
(test mode)
Interpolator
Interpolator
ADC
ADC
DAC
DAC
Multiplexer
IN1L
IN2L
IN3L
IN4L
IN5
MIC
Stereo Mix/L
Mono Mix
Multiplexer
Mono Mix
MIC
IN5
IN1R
IN2R
IN3R
IN4R
IN4R
IN3R
IN2R
IN1R
IN4L
IN3L
IN2L
IN1L
MIC
Stereo Mix/R
Mixer
IN5
Mono Mix
Mixer
IN6
Mixer
−6
dB
Stereo Mix/L
Stereo Mix/R
MIC
Mixer
−6
dB
Mixer
Mixer
MC20
0 dB/
20 dB
MIX
MS
MONO_OUT
OUTL
DACL
DAC MONO
Analog input pins
Analog output pins
Remark
The MS and MIX blocks are selectors.
2
Data Sheet S15003EJ6V0DS
OUTR
IN6
IN1R
IN2R
IN3R
IN4R
DACR
MIC1
MIC2
IN1L
IN2L
IN3L
IN4L
IN5
µ
PD63335
PIN CONFIGURATION (TOP VIEW)
48-pin plastic TQFP (fine pitch) (7 × 7)
µ
PD63335GA-9EU
MONO_OUT
37
36
35
34
33
32
31
30
29
28
27
26
25
MSWDT
MSRDT
MSCLK
TEST2
TEST1
DACR
DACL
39
DV
DD3
48
47
46
45
44
43
42
41
40
38
DV
DD1
XTL_IN
XTL_OUT
DV
SS1
SI
BIT_CLK
DV
SS2
SO
DV
DD2
LRCLK
RESET
IN6
1
2
3
4
5
6
7
8
9
10
11
12
AV
DD2
AV
SS2
NC
OUTR
OUTL
NC
NC
NC
NC
AFILT2
AFILT1
NC
Vref
AV
SS1
AV
DD1
13
14
15
16
17
18
19
20
21
22
23
24
IN3R
IN2L
IN2R
IN1L
IN1_GND
IN1R
IN4L
MIC2
MIC1
IN4R
IN3L
IN5
Data Sheet S15003EJ6V0DS
3
µ
PD63335
PIN FUNCTIONS
(1/2)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Symbol
DV
DD1
XTL_IN
XTL_OUT
DV
SS1
SI
BIT_CLK
DV
SS2
SO
DV
DD2
LRCLK
_______
RESET
IN6
IN5
IN3L
IN3R
IN2L
IN2R
IN1L
IN1_GND
IN1R
MIC1
MIC2
IN4L
IN4R
AV
DD1
AV
SS1
Vref
NC
AFILT1
AFILT2
NC
NC
NC
NC
I/O
I
O
I
I/O
O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
Digital power supply
Crystal resonator connection pin/external master clock input (see
1.3 Clock)
Crystal resonator connection pin. Leave this pin open when using an external master
clock.
Digital ground
Data input for serial data interface
Note
Bit sync clock for serial data interface
Note
Digital ground
Data output for serial data interface
Digital power supply
Frame sync clock for serial data interface
Note
Reset signal input. Sets reset mode when low.
Analog audio monaural input 6
Analog audio monaural input 5
Analog audio input 3, L channel
Analog audio input 3, R channel
Analog audio input 2, L channel
Analog audio input 2, R channel
Analog audio input 1, L channel
AC ground pin for IN1. Generally connect to AV
SS
via a 1
µ
F capacitor.
Analog audio input 1, R channel
MIC input 1
MIC input 2
Analog audio input 4, L channel
Analog audio input 4, R channel
Analog power supply
Analog ground
Reference voltage output for connecting bypass capacitor
Not used. Leave this pin open.
ADC L channel anti alias filter pin
ADC R channel anti alias filter pin
Not used. Leave this pin open.
Not used. Leave this pin open.
Not used. Leave this pin open.
Not used. Leave this pin open.
Function
Note
The SI, BIT_CLK, and LRCLK pins are neither pulled up nor pulled down within the LSI. Since malfunction
may occur if these pins are somehow set to high impedance, pull-up or pull-down should be performed
externally, via a resistor.
4
Data Sheet S15003EJ6V0DS
µ
PD63335
(2/2)
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
OUTL
OUTR
MONO_OUT
AV
DD2
DACL
NC
DACR
AV
SS2
TEST1
TEST2
MSCLK
MSWDT
MSRDT
DV
DD3
I/O
O
O
O
O
O
I
I
O
Analog audio output pin, L channel
Analog audio output pin, R channel
Analog audio monaural output
Analog power supply
Analog DAC signal output, L channel
Not used. Leave this pin open.
Analog DAC signal output, R channel
Analog ground
Test pin for IC sorting. Leave this pin open.
Test pin for IC sorting. Leave this pin open.
Sync clock input for serial command interface
Input for serial command interface
Output for serial command interface
Digital power supply
Function
Data Sheet S15003EJ6V0DS
5
AT32F425-Evaluation Report-Keil Development Environment Construction 01
Brief description: This series is based on the evaluation report of the Ateli-AT32F425R8T7-7 development board1. Keil development environment construction-lighting ceremony- DownloadYatli official web...
维尔瓦 Domestic Chip Exchange
STM32-FSMC-LCD Detailed Explanation
/*From the Internet, not original*/ [align=left]STM32-FSMC-LCD Detailed Explanation[/align][align=left][color=#454545][font="][size=10.5pt]LCD[/size][/font][/color][color=#454545][font=宋体][size=10.5pt...
568760310 stm32/stm8
f2812 SCI RS485 Debug
1. Recently, when I was debugging RS485 with sci, I encountered a strange phenomenon:sometimes (not all of the time, usually when reloading the program) the CPU clearly sent out data, the SCIRX and SC...
jk_3333 Microcontroller MCU
Brief Introduction to Lightning Protection Technology for Surveillance Television Systems
1. Introduction to Closed Circuit Television System: CCTV System Structure: CCTV monitoring system (Closed Circuit Television, referred to as CCTV), generally consists of the following three parts: Fr...
clj2004000 Industrial Control Electronics
How to use an amplifier to convert a voltage of 0.66v-2.64v to 0-5v?
I recently encountered a problem when studying: the sensor output (analog) voltage is 0.66v-2.64v. If I want to use an amplifier to convert it to the 0-5v voltage range of the A/D interface, how shoul...
pydacheng Analog electronics
Wideband ADC front-end design considerations: Should I use an amplifier or a transformer to drive the ADC?
[i=s]This post was last edited by feaeaw on 2014-7-25 16:12[/i] [size=3][color=#ff0000][b]Reposted from ADI Chinese Technical Support Forum: [url=http://ezchina.analog.com/thread/8605]http://ezchina.a...
feaeaw Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2929  1025  2394  358  2736  59  21  49  8  56 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号