ISSUED DATE :2006/06/14
REVISED DATE :
GSC93BC46/56/66
3-wire Serial EEPROMs 1K/2K/4K
The GSC93BC family provides 1K, 2K and 4K of serial electrically erasable and programmable read-only
memory (EEPROM). The wide Vdd range allows for low-voltage operation down to 1.8V and up to 5.5V. The
device, fabricated using traditional CMOS EEPROM technology, is optimized for many industrial and
commercial applications where low-voltage and low-power operation is essential. The device is accessed via a
3-wire serial interface.
Description
Features
&
Internally organized as 128x8 or 64x16 (1K),
Package Dimensions
256x8 or 128x16 (2K), 512x8 or 256x16 (4K)
&Wide-voltage range operation: 1.8V~5.5V
&3-wire serial interface bus
&Date retention: 100years
‡
&
High endurance: 1,000,000 Write Cycles
&2MHz (5V) clock rate
&Sequential read operation
&Self-timed write cycle (10ms max)
REF.
A
B
C
D
E
F
Millimeter
Min.
Max.
5.80
4.80
3.80
0°
0.40
0.19
6.20
5.00
4.00
8°
0.90
0.25
REF.
M
H
L
J
K
G
Millimeter
Min.
Max.
0.10
0.25
0.35
0.49
1.35
1.75
0.375 REF.
45°
1.27 TYP.
Figure 1. Pin Configurations
Pin Name
CS
SK
DI
DO
Gnd
Vcc
ORG
NC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
No Connect
Unit
V
V
mA
:
:
Parameter
Voltage on Any Pin with Respect to Ground
Maximum Operating Voltage
DC Output Current
Operating Temperature Range
Storage Temperature Range
Absolute Maximum Ratings
Ratings
-1.0 to Vcc +7.0
6.25
5.0
-55 ~ +125
-65 ~ +150
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
GSC93BC46/56/66
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ISSUED DATE :2006/06/14
REVISED DATE :
Figure 2. Block Diagram
Notes
1. The ORG pin is used to select between x8
and x16.
When the pin is connected to Vcc, x16 mode
is selected.
Otherwise, the ORG pin should be grounded
in order to select x8 mode.
The interface foe the GSC93BC46/56/66 is accessed through four different signals:
Chip Select (CS), Data Input (DI), Data Output (DO), and Serial Data Clock (SK). The Chip Select (CS) signal
must be pulled high before issuing a command through the Data Input (DI) pin. The Serial Data Clock (SK)
signal is used in conjunction with the Data Input (DI) pin.
Applicable over recommended operating range from T
A
=25 : , f=1.0MHz, Vcc=+5V
Symbol
Test Condition
Max
Unit
C
OUT
Output Capacitance (DO)
5
pF
C
IN
Input Capacitance (CK, SK, DI)
5
pF
Note: 1. This parameter is characterized and not 100% tested.
PIN Capacitance
Condition
V
OUT
=0V
V
IN
=0V
DC Characteristics
Applicable over recommended operating range from: T
A
=-40 ~ +85 : , Vcc=+1.8 ~ +5V
(unless
otherwise noted)
Parameter
Symbol
Test Condition
Min
TYP
Max
Unit
Supply Voltage
V
CC1
1.8
-
5.5
V
Supply Voltage
V
CC2
2.7
-
5.5
V
Supply Voltage
V
CC3
4.5
-
5.5
V
Supply Current V
CC
=5.0V
I
CC
READ at 1MHz
-
0.5
2.0
mA
Supply Current V
CC
=5.0V
I
CC
WRITE at 1MHz
-
0.5
2.0
mA
Standby Current V
CC
=1.8V
I
SB1
CS=0V
-
0
0.1
A
Standby Current V
CC
=2.7V
I
SB2
CS=0V
-
6.0
10.0
A
Standby Current V
CC
=5.0V
I
SB3
CS=0V
-
17
30
A
Input Leakage Current
I
LI
V
IN
=0V to V
CC
-
0.1
3.0
A
Output Leakage Current
I
LO
V
IN
=0V to V
CC
-
0.1
3.0
A
(1)
-0.6
0.8
Input Low Level
V
IL1
2.7V< V
CC
<5.5V
-
V
(1)
2.0
V
CC
+1
Input High Level
V
IH1
-0.6
V
CC
x0.3
Input Low Level
V
IL2
(1)
1.8V< V
CC
<2.7V
-
V
(1)
V
CC
x0.7
Input High Level
V
IH2
V
CC
+1
0.4
Output Low Level
V
OL1
(1)
2.7V< V
CC
<5.5V; I
OL
=2.1mA
-
V
-
(1)
-
Output High Level
V
OH1
I
OH
=-0.4mA
2.4
0.2
Output Low Level
V
OL2
(1)
1.8V< V
CC
<2.7V; I
OL
=0.15mA
-
-
V
(1)
-
Output High Level
V
OH2
I
OH
=-100uA V
CC
-2
Note 1: V
IL
and V
IH
max are reference only and are not tested.
GSC93BC46/56/66
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ISSUED DATE :2006/06/14
REVISED DATE :
AC Characteristics
Applicable over recommended operating range from: T
A
=-40 ~ +85 : , Vcc=As specified, C
L
=1 TTL Gate &
100pF
(unless
otherwise noted)
Parameter
Symbol
Test Condition
Min
TYP
Max
Unit
Clock Frequency, SK
f
SK
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
Relative
To SK
Relative
To SK
Relative
To SK
Relative
To SK
AC Test
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
4.5V< V
CC
<5.5V
2.7V< V
CC
<5.5V
1.8V< V
CC
<5.5V
0
0
0
250
250
1000
250
250
1000
250
250
1000
50
50
200
100
100
400
0
100
100
400
-
-
2
1
0.25
-
MHz
SK High Time
t
SKH
-
ns
SK Low Time
t
SKL
-
-
ns
Minimum CS Low Time
t
CS
-
-
ns
CS Setup Time
t
CSS
-
-
ns
DI Setup Time
CS Hold Time
DI Hold Time
t
DIS
t
CSH
t
DIH
-
-
-
-
-
-
250
250
1000
250
250
1000
250
250
1000
100
100
400
10
-
ns
ns
ns
Output Delay to “1”
t
PD1
-
ns
Output Delay to “0”
t
PD0
AC Test
-
-
ns
CS to Status Valid
t
SV
AC Test
AC Test
CS=V
IL
-
-
ns
CS to DO in High Impedance
Write Cycle Time
5.0V, 25 :
t
DF
t
WP
Endurance
(1)
-
-
1M
-
3
-
ns
ms
Write
Cycles
Note: 1. This parameter is characterized and not 100% tested.
GSC93BC46/56/66
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ISSUED DATE :2006/06/14
REVISED DATE :
Instruction set for the GSC93BC46
Instruction SB
READ
EWEN
ERASE
WRITE
ERAL
WRAL
EWDS
1
1
1
1
1
1
1
Address
OP
Code X8
10
00
11
01
00
00
00
A
6
~ A
0
11xxxxx
A
6
~ A
0
A
6
~ A
0
10xxxxx
01xxxxx
00xxxxx
X16
A
5
~ A
0
11xxxx
A
5
~ A
0
A
5
~ A
0
10xxxx
01xxxx
00xxxx
D
7
~ D
0
D
15
~ D
0
Data
X8
X16
Comment
Reads data stored at specified
memory location.
Write enable command (must be
issued before any erase or write
operation).
Erases memory location A
n
~A
0
Write to memory location A
n
~A
0
Erases all memory locations.
Valid only at V
CC
=4.5V to 5.5V
Write all memory locations.
Valid only at V
CC
=4.5V to 5.5V
Disables all erase or write
instructions
D
7
~ D
0
D
15
~ D
0
Note : The X’s in the address field represent don’t care values and must be clocked.
Instruction set for the GSC93BC56/66
Instruction SB
READ
EWEN
ERASE
WRITE
ERAL
WRAL
EWDS
1
1
1
1
1
1
1
Address
OP
Code X8
10
00
11
01
00
00
00
A
8
~ A
0
X16
A
7
~ A
0
Data
X8
X16
Comment
Reads data stored at specified
memory location.
Write enable command (must be
issued before any erase or write
operation).
Erases memory location A
n
~A
0
Write to memory location A
n
~A
0
Erases all memory locations.
Valid only at V
CC
=4.5V to 5.5V
Write all memory locations.
Valid only at V
CC
=4.5V to 5.5V
Disables all erase or write
instructions
11xxxxxxx 11xxxxxx
A
8
~ A
0
A
8
~ A
0
A
7
~ A
0
A
7
~ A
0
D
7
~D
0
D
15
~D
0
10xxxxxxx 10xxxxxx
01xxxxxxx 01xxxxxx
00xxxxxxx 00xxxxxx
D
7
~D
0
D
15
~D
0
Note : The X’s in the address field represent don’t care values and must be clocked.
Function Description
The GSC93BC46/56/66 support 7 different instructions, which must be clocked serially using the CS, SK and
DI pins. Before sending each of these instructions, the CS pin must be pulled high followed by a START bit
(logic ‘1’). The next sequence includes a 2-bit Op Code and usually an 8 or 16-bit address. The next
description describes the various functions in the chip.
READ (READ):
The Read (READ) instruction includes the Op Code (“10”) followed by the memory address
location to be read. After the instruction and address is sent, the data from the memory location can be clocked
out using the serial output pin DO. The data changes on the rising edge of the clock, so the falling edge can be
used to strobe the output.
Note that during shifting the last address bit, the DO pin is a dummy bit (logic “0”).
ERASE/WRITE (EWEN)):
When the chip is first powered-on, no erase or write instructions can be issued.
Only when the Erase/Write Enable (EWEN) instruction is sent will the system be allowed to write to the chip.
The EWEN command only needs to be issued once after being powered-on. To disable the chip again, the
Erase/Write Disable (EWDS) command can be used.
GSC93BC46/56/66
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ISSUED DATE :2006/06/14
REVISED DATE :
ERASE (ERASE):
The Erase (ERASE) instruction clears the designated memory location to a logic ‘1’ state.
After the Op Code and address location is inputted, the chip will enter into an erase cycle. When the cycle
completes, the chip will automatically enter into standby mode.
WRITE (WRITE):
The Write (WRITE) instruction is used to write to a specific memory location. If word mode
(x16) is selected, then 16 bits of data will be written into the location. If byte mode (x8) is chosen, then 8 bits of
data will be written into the location. The write cycle will begin automatically after the 8 or 16 bits are shifted
into the chip.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction is primarily used for testing purposes and only
functions when V
CC
=4.5V to 5.5V. This instruction will clear the entire memory array to ‘1’.
WRITE ALL (WRAL):
The Write All (WRAL) instruction will program the entire memory array according to the 8
or 16-bit data pattern provided. The instruction will only be valid when V
CC
=4.5V to 5.5V.
ERASE/WRITE DISABLE (EWDS):
The Erase/Write Disable (EWDS) instruction blocks any kind of erase or
program operations from modifying the contents of the memory array. This instruction should be executed after
erasing or programming to prevent accidental data loss.
Note also that the READ instruction will operate regardless of whether the chip is disabled from program and
write operations.
To determine whether the chip has completed an erase or write operation, the CS signal can be pulled LOW
for a minimum of 250ns (t
CS
) and then pulled back HIGH to enter Ready/Busy mode. If the chip is currently in
the programming cycle, t
WP
, then the DO pin will go low (logical “0”). When the write cycle completes, the DO
pin is pulled high (logical “1”) to indicate that the part can receive anther instruction. Note that the Ready/Busy
polling cannot be done if the chip has already finished and returned back to standby mode.
Ready/Busy
Timing Diagrams
Synchronous Data Timing
Note (1): This is the minimum SK period.
Organization Key for TIMING Diagrams
I/O
A
N
D
N
GSC93BC46(1K)
X8
X16
A
6
A
5
D
7
D
15
GSC93BC56(2K)
X8
X16
(1)
A
8
A
7
(2)
D
7
D
15
GSC93BC66(4K)
X8
X16
A
8
A
7
D
7
D
15
Note:
1. A
8
is a DON’T CARE value, but the extra clock is required.
2. A
7
is a DON’T CARE value, but the extra clock is required.
GSC93BC46/56/66
Page: 5/8
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