GS4576C09L-24I datasheet, PDF - EEWORLD Datasheet

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GS4576C09L-24I: DescriptionDDR DRAM, 64MX9, CMOS, PBGA144, UBGA-144; Categorystorage storage; File Size2MB，62 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS4576C09L-24I Overview

DDR DRAM, 64MX9, CMOS, PBGA144, UBGA-144

GS4576C09L-24I Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	144
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B144
length	18.5 mm
memory density	603979776 bit
Memory IC Type	DDR DRAM
memory width	9
Number of functions	1
Number of ports	1
Number of terminals	144
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX9
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	11 mm

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GS4576C09/18/36L

144-Ball

BGA

Commercial Temp

Industrial Temp

Features

• Pin- and function-compatible with Micron RLDRAM® II

• 533 MHz DDR operation (1.067Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)

• 16M x 36, 32M x 18, and 64M x 9 organizations available

• 8 banks

• Reduced cycle time (15 ns at 533 MHz)

• Address Multiplexing (Nonmultiplexed address option

available)

• SRAM-type interface

• Programmable Read Latency (RL), row cycle time, and burst

sequence length

• Balanced Read and Write Latencies in order to optimize data

bus utilization

• Data mask for Write commands

• Differential input clocks (CK, CK)

• Differential input data clocks (DKx, DKx)

• On-chip DLL generates CK edge-aligned data and output

data clock signals

• Data valid signal (QVLD)

• 32 ms refresh (16K refresh for each bank; 128K refresh

command must be issued in total each 32 ms)

• 144-ball

BGA

package

• HSTL I/O (1.5 V or 1.8 V nominal)

• 25–60 matched impedance outputs

• 2.5 V V

EXT

, 1.8 V V

, 1.5 V or 1.8 V V

DDQ

I/O

• On-die termination (ODT) R

• Commerical and Industrial Temperature

Commercial (+0°

T

+95°C)

Industrial (–40°

T

+95°C)

64M x 9, 32M x 18, 16M x 36

576Mb CIO Low Latency DRAM (LLDRAM II)

Introduction

533 MHz–300 MHz

2.5 V V

EXT

1.8 V V

1.5 V or 1.8 V V

DDQ

The GSI Technology 576Mb Low Latency DRAM



(LLDRAM II) is a high speed memory device designed for

high address rate data processing typically found in networking

and telecommunications applications. The 8-bank architecture

and low tRC allows access rates formerly only found in

SRAMs.

The Double Data Rate (DDR) I/O interface provides high

bandwidth data transfers, clocking out two beats of data per

clock cycle at the I/O balls. Source-synchronous clocking can

be implemented on the host device with the provided free-

running data output clock.

Commands, addresses, and control signals are single data rate

signals clocked in by the True differential input clock

transition, while input data is clocked in on both crossings of

the input data clock(s).

Read and Write data transfers always in short bursts. The burst

length is programmable to 2, 4 or 8 by setting the Mode

The device is supplied with 2.5 V V

EXT

and 1.8 V V

for the

core, and 1.5 V or 1.8 V for the HSTL output drivers.

Internally generated row addresses facilitate bank-scheduled

refresh.

The device is delivered in an efficent

BGA

144-ball package.

Rev: 1.04 11/2013

1/62

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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