The QS5810 is a high speed, low noise 1-10 non-inverting buffer
designed for SDRAM clock buffer applications. Out of the 10 outputs,8 could
be used to drive up to four SDRAM SO-DIMMS, and the remaining can be
used for external feedback to a PLL stage for synchronization to master
clock.
The QS5810 also includes an I
2
C interface, which can enable or disable
each output clock driver. By turning the outputs on and off, I
2
C will aid in
reducing the Electro Magnetic Interference (EMI).
FUNCTIONAL BLOCK DIAGRAM
SDRAM 0
SDRAM 1
SDRAM 2
SDATA
I2 C
DECODING
I/O PORT
SDRAM 3
SDRAM 4
SDRAM 5
SDRAM 6
BUF_IN
SDRAM 7
SDRAM 8
SDRAM 9
OE
SCLK
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
APRIL 2000
DSC-5474/-
QS5810
LOW SKEW CLOCK DRIVER/BUFFER FOR MOBILE PC
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Output Voltage V
IN
DC Input Diode Current with V
I
< 0
Maximum Power Dissipation at T
A
= 85°C
T
STG
Storage Temperature
Max.
– 0.5 to 4.6V
– 0.5 to + 4.6V
– 0.5 to + 4.6
– 20
600
–65 to 150
Unit
V
V
V
mA
mW
°C
V
DD
SDRAM 0
SDRAM 1
GND
V
DD
SDRAM 2
SDRAM 3
GND
BUF_IN
V
DD
SDRAM 8
GND
V
DD
I
2
C
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
SDRAM 7
SDRAM 6
GND
V
DD
SDRAM 5
SDRAM 4
GND
OE
V
DD
SDRAM 9
GND
GNDI
2
C
SCLK
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
SSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
SDRAM (0:3)
SDRAM (4:7)
SDRAM (8:9)
BUF_IN
SDATA
SCLK
OE
V
DD
GND
GNDI
2
C
V
DD
I
2
C
Description
SDRAM Byte 0 Clock Outputs.
SDRAM Byte 1 Clock Outputs.
SDRAM Byte 2 Clock Outputs.
Input for Buffers.
I
2
C Data Input. It has 100kΩ internal pull up to V
DD
.
I
2
C Data Input. It has 100kΩ internal pull up to V
DD
.
Tri-State Output Enable. When asserted LOW, clock outputs are high impedance. It has 100kΩ internal pull up to V
DD
.
3.3V power supply for output buffers.
Ground for output buffers.
Ground for I
2
C circuitry.
3.3V Power Supply for I
2
C circuitry.
2
QS5810
LOW SKEW CLOCK DRIVER/BUFFER FOR MOBILE PC
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input High Current
Input Low Current
Test Conditions
For all Inputs
For all inputs except I
2
C inputs (SDATA and SCLK)
I
2
C Inputs (SDATA and SCLK)
V
IN
= V
DD
V
IN
= 0V: BUF_IN
V
IN
= 0V; OE, SDATA, SCLK
C
L
= 0pF; f
IN
@66.66MHz
(1)
C
L
= 0pF; f
IN
@100MHz
(1)
I
DD
Supply Current
C
L
= 30pF; f
IN
@66.66MHz
(1)
C
L
= 30pF; f
IN
@100MHz
(1)
BUF_IN 0 = GND or V
DD,
all other inputs to V
DD
V
OH
V
OL
V
OL
I
2
C
Output High Voltage
Output Low Voltage
Output Low Voltage
SDRAM (0:9) I
OH
= -36mA
SDRAM (0:9) I
OL
= 25mA
Min.
2
—
—
–5
–5
– 100
—
—
—
—
—
2.4
—
—
Typ.
(1)
—
—
—
—
—
—
50
75
110
165
—
—
—
—
Max.
—
0.8
0.7
5
5
0
70
105
130
195
500
—
0.4
µA
V
V
V
mA
µA
µA
Unit
V
V
SDATA I
OLI
2
C
= 3mA
0.4
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
R
T
f
D
t
Parameter
Rise
Time
(1)
Fall Time
(1)
Duty Cycle
(1)
Skew (output-output)
(1)
Propagation Delay
Enable Delay, OE to SDRAM
Disable Delay, OE to SDRAM
Test Conditions
0.4V to 2.4V; C
L
= 30pF
2.4V to 0.4V; C
L
= 30pF
V
T
= 1.5V; C
L
= 30pF, with 50% Input Clock
V
T
= 1.5V; C
L
= 30pF for all outputs
V
T
= 1.5V
V
T
= 1.5V
V
T
= 1.5V
Min.
—
—
45
—
—
—
—
Typ.
(1)
—
—
50
—
—
—
—
Max.
2.2
2.2
55
200
6
8
8
Unit
ns
ns
%
ps
ns
ns
ns
T
SK
T
PHL or
T
PLH
T
PZL or
T
PZH
T
PLZ or
T
PHZ
OPERATING CHARACTERISTICS , T
A
= 25oC
Symbol
V
DD
T
A
C
L
C
IN
Parameter
Power Supply Voltage
Operating Temperature
Load Capacitance
Input Capacitance
Min.
3.135
-40
—
—
Typ.
3.3
25
—
—
Max.
3.465
85
30
15
Unit
V
°C
pF
pF
3
QS5810
LOW SKEW CLOCK DRIVER/BUFFER FOR MOBILE PC
INDUSTRIAL TEMPERATURE RANGE
I
2
C SERIAL INTERFACE CONTROL
The I
2
C interface permits individual enable/disable of each clock output: any unused outputs may be disabled to reduce the EMI. The QS5810 is a
slave receiver device. It can read back the data stored in the latches for verification.
The data transfer rate supported by the I
2
C interface is 100k bits/sec. Data is transferred in bytes (with the addition of start, stop, acknowledge bits)
in sequential order from the lowest to highest byte with the ability to stop after any complete byte has been transferred. The first two bytes transferred
must be a Command Code followed by a Byte Count. Both of these bytes are ignored by the device.
The I
2
C address of the QS5810 is:
A7
1
A6
1
A5
0
A4
1
A3
0
A2
0
A1
1
Address A0 is the read/write bit and is set to 0 for writes and 1 for reads. During read back, the first byte read is a Byte Count representing the number
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