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TZA3014V

Description
IC ATM/SONET/SDH SUPPORT CIRCUIT, PBCC32, 5 X 5 MM, 0.65 MM HEIGHT, HEAT SINK, PLASTIC, MO-127, SOT-560-1, BCC-32, ATM/SONET/SDH IC
CategoryWireless rf/communication    Telecom circuit   
File Size165KB,28 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

TZA3014V Overview

IC ATM/SONET/SDH SUPPORT CIRCUIT, PBCC32, 5 X 5 MM, 0.65 MM HEIGHT, HEAT SINK, PLASTIC, MO-127, SOT-560-1, BCC-32, ATM/SONET/SDH IC

TZA3014V Parametric

Parameter NameAttribute value
MakerNXP
Parts packaging codeBCC
package instructionHVBCC,
Contacts32
Manufacturer packaging codeSOT-560-1
Reach Compliance Codeunknown
JESD-30 codeS-PBCC-B32
length5 mm
Negative supply voltage rating-3.3 V
Number of functions1
Number of terminals32
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeHVBCC
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification statusNot Qualified
Maximum seat height0.8 mm
surface mountYES
Telecom integrated circuit typesATM/SONET/SDH SUPPORT CIRCUIT
Temperature levelINDUSTRIAL
Terminal formBUTT
Terminal pitch0.5 mm
Terminal locationBOTTOM
width5 mm

TZA3014V Preview

INTEGRATED CIRCUITS
DATA SHEET
TZA3014
2.5 Gbits/s postamplifier with level
detector
Preliminary specification
File under Integrated Circuits, IC19
2000 Aug 09
Philips Semiconductors
Preliminary specification
2.5 Gbits/s postamplifier with level detector
FEATURES
Single 3.3 V power supply
Wideband operation from 50 kHz to 2.5 GHz (typical
value)
Fully differential
On-chip DC-offset compensation without external
capacitor
Interfaces with supplied positive or negative logic
Positive Emitter Coupled Logic (PECL) or Current-Mode
Logic (CML) compatible data outputs adjustable from
200 to 800 mV (p-p) single-ended
Power-down capability for unused output or detector
Rise and fall times of 80 ps (typical value)
Inverted output possible
Input level detection circuit for Received Signal Strength
Indicator (RSSI) and Loss Of Signal (LOS),
programmable from 0.4 to 400 mV (p-p) single-ended,
with open-drain comparator output for directly
interfacing positive or negative logic
Reference voltage for output level and LOS adjustment
HTQFP32 and HBCC32 plastic packages with exposed
pad
Mute input.
ORDERING INFORMATION
TYPE
NUMBER
TZA3014HT
TZA3014V
TZA3014U
PACKAGE
NAME
HTQFP32
HBCC32
DESCRIPTION
plastic, heatsink thin quad flat package; 32 leads; body 5
×
5
×
1.0 mm
APPLICATIONS
TZA3014
Postamplifier for SDH/SONET transponder
SDH/SONET wavelength converter
PECL driver
Fibre channel arbitrated loop
Signal level detectors
Swing converter CML 200 mV (p-p) to
PECL 800 mV (p-p)
2.5 GHz clock amplification.
GENERAL DESCRIPTION
The TZA3014 is a low gain postamplifier with a LOS
detector and a RSSI designed for use in critical signal path
control applications, such as loop-through or Wavelength
Division Multiplexing (WDM). The signal path is capable of
operating from 50 kHz up to 2.5 GHz.
The TZA3014 can be delivered in HTQFP32 and HBCC32
packages.
VERSION
SOT547-2
SOT560-1
plastic, heatsink bottom chip carrier; 32 terminals; body 5
×
5
×
0.65 mm
bare die; 2.22
×
2.22
×
0.38 mm
2000 Aug 09
2
Philips Semiconductors
Preliminary specification
2.5 Gbits/s postamplifier with level detector
BLOCK DIAGRAM
TZA3014
handbook, full pagewidth
VEEA
LOSTH
32 (40)
10 (12)
disable LOS output
comparator
(31) 25
VEEB
RSSI
offset compensation
5 kΩ
(35) 27
(34) 26
LOS
RSSI
offset compensation
LEVEL
INV
GNDA
IN
INQ
GNDA
12 (15)
29 (37)
1
2
3
4
cross-over
switch
level
(30) 24
(29) 23
(28) 22
buffer
amplifier
(27) 21
GNDB
OUT
OUTQ
GNDB
TEST
MUTE
15 (19)
31 (39)
TZA3014
BAND GAP
REFERENCE
(17) 14
Vref
MGU122
The numbers in parentheses refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
2000 Aug 09
3
Philips Semiconductors
Preliminary specification
2.5 Gbits/s postamplifier with level detector
PINNING
SYMBOL
GNDA
IN
INQ
GNDA
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
LOSTH
PIN
1
2
3
4
5
6
7
8
9
10
PAD
1
2
3
4
5
6
7
8
9
10
11
12
TYPE
(1)
S
I
I
S
I
I
S
S
I
DESCRIPTION
ground for input and LOS detector
TZA3014
differential input; complimentary to pin INQ; DC bias level is set internally
at approximately
−0.33
V
differential input; complimentary to pin IN; DC bias level is set internally at
approximately
−0.33
V
ground for input and LOS detector
not connected
not connected
not connected
not connected
not connected
not connected
not connected
input for setting threshold level of LOS detector; threshold level is set by
connecting external resistors between pins GNDA and V
ref
. When forced to
V
EEA
or not connected, the LOS detector is switched off.
not connected
not connected
input for setting AC level of the output circuit; output signal level is set by
connecting external resistors between pins GNDA and V
ref
. When forced to
GNDA or not connected, pins OUT and OUTQ will be switched off.
not connected
reference voltage for programming output level circuit and LOS threshold;
typical value is
−1.6
V; no external capacitor allowed
not connected
for test purposes only; to be left open-circuit in the application
not connected
not connected
not connected
not connected
not connected
not connected
not connected
ground for output circuit
PECL or CML compatible differential output; complimentary to pin OUT
PECL or CML compatible differential output; complimentary to pin OUTQ
ground for output circuit
negative supply voltage for output circuit
not connected
n.c.
n.c.
LEVEL
11
12
13
14
15
I
I
n.c.
V
ref
n.c.
TEST
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
GNDB
OUTQ
OUT
GNDB
V
EEB
n.c.
n.c.
13
14
15
16
17
18
19
20
21
22
23
24
25
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
O
I
S
S
O
O
S
S
O
O
S
S
O
O-DRN not connected
2000 Aug 09
4
Philips Semiconductors
Preliminary specification
2.5 Gbits/s postamplifier with level detector
TZA3014
SYMBOL
RSSI
LOS
n.c.
INV
n.c.
MUTE
V
EEA
V
EEP
Note
PIN
26
27
28
29
30
31
32
pad
PAD
34
35
36
37
38
39
40
TYPE
(1)
O
RSSI output
DESCRIPTION
O-DRN output of LOS detector; direct drive to either positive or negative supplied
logic via internal 5 kΩ resistor
TTL
TTL
TTL
TTL
S
S
not connected
input to invert the signal at pins OUT and OUTQ; supports positive or
negative logic
not connected
input to mute the output signal on pins OUT (‘0’) and OUTQ (‘1’); supports
positive or negative logic
negative supply voltage for input and LOS detector
negative supply voltage pad (exposed die pad)
1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.
31 MUTE
GNDA
IN
INQ
GNDA
n.c.
n.c.
n.c.
n.c.
1
2
3
4
exposed pad
27 LOS
29 INV
30 n.c.
28 n.c.
handbook, full pagewidth
25 VEEB
32 VEEA
26 RSSI
24 GNDB
23 OUT
22 OUTQ
21 GNDB
TZA3014HT
5
6
7
8
VEEP
20 n.c.
19 n.c.
18 n.c.
17 n.c.
LOSTH 10
n.c. 11
LEVEL 12
n.c. 13
Vref 14
TEST 15
n.c. 16
n.c. 9
MGU123
Fig.2 Pin configuration HTQFP32.
2000 Aug 09
5
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