CILETIV LESOM
V54C365324V
Clock Frequency (t
CK
)
CAS Latency
Cycle Time (t
CK
)
Access Time (t
AC
)
V54C365324V
200/183/166/143 MHz 3.3 VOLT
ULTRA HIGH PERFORMANCE
2M X 32 SDRAM 4 BANKS X 512Kbit X 32
PRELIMINARY
-5
200
3
5
5
-55
183
3
5.5
5.5
-6
166
3
6
6
-7
143
3
7
6
-8
125
3
8
6
Unit
MHz
clocks
ns
ns
Features
s
JEDEC Standard 3.3V Power Supply
s
The V54C365324V is ideally suited for high
performance graphics peripheral applications
s
Single Pulsed RAS Interface
s
Programmable CAS Latency: 2, 3
s
All Inputs are sampled at the positive going edge
of clock
s
Programmable Wrap Sequence: Sequential or
Interleave
s
Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
s
DQM 0-3 for Byte Masking
s
Auto & Self Refresh
s
2K Refresh Cycles/32 ms
s
Burst Read with Single Write Operation
Description
The V54C365324V is a 67,108, 864 bits synchro-
nous high data rate DRAM organized as 4 x
524,288 words by 32 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
V54C365324V Rev. 1.2 August 2001
1
V54C365324V
PIN CONFIGURATION
CILETIV LESOM
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DD
DQM
0
WE
CAS
RAS
CS
NC
BA0
BA1
A
10
/AP
A
0
A
1
A
2
DQM
2
V
DD
NC
DQ
16
V
SSQ
DQ
17
DQ
18
V
DDQ
DQ
19
DQ
20
V
SSQ
DQ
21
DQ
22
V
DDQ
DQ
23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V54C365324V Rev. 1.2 August 2001
86 Pin TSOP (II)
(400mil x 875mil)
(0.5mm Pin pitch)
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SS
DQM
1
NC
NC
CLK
CKE
A9
A8
A
7
A
6
A
5
A
4
A
3
DQM
3
V
SS
NC
DQ
31
V
DDQ
DQ
30
DQ29
V
SSQ
DQ
28
DQ
27
V
DDQ
DQ
26
DQ
25
V
SSQ
DQ
24
V
SS
2
V54C365324V
DQMi
Column Decoder
RAS
CAS
WE
DQMi
Timing
Register
Row
Decoder
Row Address
Buffer
Column Address
Counter
Latency &
Burst Length
CLK
Programming
Register
A
0
-A
10
, BA0, BA1
Column Address
Buffer
Row Addresses
Refresh
Counter
Address
A
0
-A
7
Column Addresses
V54C365324V Rev. 1.2 August 2001
3
Output
Buffer
CLK
CKE
CS
Sense Amplifier
DQMi
Bank0
512K x 32
Bank1
512K x 32
Bank2
512K x 32
Bank3
512K x 32
Input
Buffer
CILETIV LESOM
Block Diagram
Write
Control
Logic
MUX
DQ
0
-DQ
31
V54C365324V
CILETIV LESOM
Pin
CLK
CKE
Signal Pin Description
Name
Clock Input
Clock Enable
Input Function
System clock input. Active on the positive rising edge to sample all inputs
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self re-
fresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low. En-
ables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A
0
-A
10
defines the row address.
During a read or write command, A
0
-A
7
defines the column address. In
addition to the column address A
10
is used to invoke auto precharge BA
define the bank to be precharged. A
10
is low, auto precharge is disabled
during a precharge cycle, If A
10
is high, all bank will be precharged, if A
10
is low, the BA0, BA1 is used to decide which bank to precharge
Selects which bank to activate.
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V ± 0.3V/ground
Provides isolated power/ground to DQs for improved noise immunity
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
A
0
-A
10
Write Enable
Address
BA
0
, BA
1
DQ
0
-DQ
31
DQMi
VDD/VSS
VDDQ/VSSQ
NC
Bank Select
Data Input/Output
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
V54C365324V Rev. 1.2 August 2001
4
V54C365324V
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200
µs
is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
V54C365324V Rev. 1.2 August 2001
CILETIV LESOM
A9
0
1
A6
0
0
0
0
1
1
1
A5
0
0
1
1
0
1
1
Address Input for Mode Set (Mode Register Operation)
A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Write Burst Length
Test
Mode
CAS Latency
BT
Burst Length
Mode Register
Write Burst Length
Length
Burst
Single Bit
Test Mode
A8
0
A7
0
Mode
Mode Reg
Set
Burst Type
A3
0
1
Type
Sequential
Interleave
CAS Latency
A4
0
1
0
1
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
Reserve
Reserve
Burst Length
Length
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
Sequential
0
1
0
1
0
1
0
1
1
2
4
8
Reserve
Reserve
Reserve
Full Page
Interleave
1
2
4
8
Reserve
Reserve
Reserve
Reserve
Power On and Initialization
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS
Latency
Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set
operation. Address input data at this timing defines
parameters to be set as shown in the previous table.
5
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