D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
Freescale Semiconductor
Technical Data
Document Number: MPC755EC
Rev. 7.0, 04/2005
MPC755
RISC Microprocessor
Hardware Specifications
This document is primarily concerned with the MPC755;
however, unless otherwise noted, all information here also
applies to the MPC745. The MPC755 and MPC745 are
reduced instruction set computing (RISC) microprocessors
that implement the PowerPC™ instruction set architecture.
This document describes pertinent physical characteristics of
the MPC755. For information on specific MPC755 part
numbers covered by this or other specifications, see
Section 10, “Ordering Information.”
For functional
characteristics of the processor, refer to the
MPC750 RISC
Microprocessor Family User’s Manual.
To locate any published errata or updates for this document,
refer to the website at http://www.freescale.com.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical and Thermal Characteristics . . . . . . . . . . . . 6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 32
System Design Information . . . . . . . . . . . . . . . . . . . 37
Document Revision History . . . . . . . . . . . . . . . . . . . 51
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 54
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
1
Overview
The MPC755 is targeted for low-cost, low-power systems
and supports the following power management
features—doze, nap, sleep, and dynamic power
management. The MPC755 consists of a processor core and
an internal L2 tag combined with a dedicated L2 cache
interface and a 60x bus. The MPC745 is identical to the
MPC755 except it does not support the L2 cache interface.
Figure 1
shows a block diagram of the MPC755.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Overview
2
Instruction Unit
Fetcher
BTIC
64-Entry
SRs
(Shadow)
IBAT
Array
ITLB
BHT
CTR
LR
128-Bit
(4 Instructions)
Branch Processing
Unit
Instruction MMU
Additional Features
Instruction Queue
(6-Word)
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
Tags
32-Kbyte
I Cache
2 Instructions
Dispatch Unit
64-Bit
(2 Instructions)
Reservation
Station
GPR File
Rename Buffers
(6)
Integer Unit 2
System Register
Unit
32-Bit
Load/Store Unit
64-Bit
Reservation
Station
Reservation
Station
Reservation Station
(2-Entry)
FPR File
Rename Buffers
(6)
Reservation Station
Integer Unit 1
+
(EA Calculation)
Store Queue
64-Bit
Floating-Point
Unit
+
×
÷
+
CR
32-Bit
+
×
÷
FPSCR
FPSCR
Figure 1. MPC755 Block Diagram
PA
Data MMU
SRs
(Original)
DBAT
Array
DTLB
32-Bit
EA
60x Bus Interface Unit
64-Bit
Instruction Fetch Queue
L1 Castout Queue
L2 Bus Interface
Unit
L2 Castout Queue
Completion Unit
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
Tags
32-Kbyte
D Cache
Data Load Queue
32-Bit Address Bus
32-/64-Bit Data Bus
17-Bit L2 Address Bus
64-Bit L2 Data Bus
Reorder Buffer
(6-Entry)
L2 Controller
L2CR
L2 Tags
Freescale Semiconductor
Not in the MPC745
Features
2
Features
This section summarizes features of the MPC755 implementation of the PowerPC architecture. Major
features of the MPC755 are as follows:
• Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating
branch delay slots
• Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, floating-point)
— Serialization control (predispatch, postdispatch, execution serialization)
• Decode
— Register file access
— Forwarding control
— Partial instruction decode
• Completion
— Six-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization, and all instruction flow changes
• Fixed point units (FXUs) that share 32 GPRs for integer operands
— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
• Floating-point unit and a 32-entry FPR file
— Support for IEEE standard 754 single- and double-precision floating-point arithmetic
— Hardware support for divide
— Hardware support for denormalized numbers
— Single-entry reservation station
— Supports non-IEEE mode for time-critical operations
— Three-cycle latency, one-cycle throughput, single-precision multiply-add
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
Freescale Semiconductor
3
Features
•
•
•
•
— Three-cycle latency, one-cycle throughput, double-precision add
— Four-cycle latency, two-cycle throughput, double-precision multiply-add
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
Load/store unit
— One-cycle load or store cache access (byte, half-word, word, double word)
— Effective address generation
— Hits under misses (one outstanding miss)
— Single-cycle unaligned access within double-word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big- and little-endian byte addressing supported
Level 1 cache structure
— 32K, 32-byte line, eight-way set-associative instruction cache (iL1)
— 32K, 32-byte line, eight-way set-associative data cache (dL1)
— Cache locking for both instruction and data caches, selectable by group of ways
— Single-cycle cache access
— Pseudo least-recently-used (PLRU) replacement
— Copy-back or write-through data cache (on a page per page basis)
— MEI data cache coherency maintained in hardware
— Nonblocking instruction and data cache (one outstanding miss under hits)
— No snooping of instruction cache
Level 2 (L2) cache interface (not implemented on MPC745)
— Internal L2 cache controller and tags; external data SRAMs
— 256K, 512K, and 1 Mbyte two-way set-associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— Instruction-only mode and data-only mode
— 64-byte (256K/512K) or 128-byte (1M) sectored line size
— Supports flow through (register-buffer) synchronous BurstRAMs, pipelined (register-register)
synchronous BurstRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late
write synchronous BurstRAMs
— L2 configurable to cache, private memory, or split cache/private memory
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
— 64-bit data bus
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
4
Freescale Semiconductor
京公网安备 11010802033920号
EEWORLD
