1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004
DATA SHEET
General Description
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a member of
HiPerClockS™
the HiPerClockS® family of High Performance Clock
Solutions from IDT. The ICS87004 has two selectable
clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. Internal bias
on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs
to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to 250MHz.
The reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
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Four LVCMOS/LVTTL outputs, 7
Ω
typical output impedance
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0
Full 3.3V or 2.5V output operating supply
5V tolerant inputs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
PLL_SEL
Pullup
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
0
1
1
Q1
Q0
0
Pin Assignment
GND
Q0
V
DDO
SEL0
SEL1
SEL2
SEL3
CLK_SEL
V
DD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q1
V
DDO
Q2
GND
Q3
V
DDO
MR
FB_IN
PLL_SEL
CLK1
nCLK1
V
DDA
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
FB_IN
Pulldown
PLL
Q2
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q3
ICS87004
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
ICS87004AG REVISION C DECEMBER 1, 2009
1
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 12, 21
2, 20,
22, 24
3, 19, 23
4, 5,
6, 7
8
9
10
11
13
14
15
16
Name
GND
Q0, Q3,
Q2, Q1
V
DDO
SEL0, SEL1,
SEL2, SEL3
CLK_SEL
V
DD
CLK0
nCLK0
V
DDA
nCLK1
CLK1
PLL_SEL
Power
Output
Power
Input
Input
Power
Input
Input
Power
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Type
Description
Power supply ground.
Single-ended clock outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,
selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Core supply pin.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Analog supply pin.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS / LVTTL interface levels.
17
FB_IN
Input
Pulldown
18
MR
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation
Capacitance (per output)
Output Impedance
V
DD
, V
DDO
= 3.465V
V
DD
, V
DDO
= 2.625V
5
7
Test Conditions
Minimum
Typical
4
51
51
23
17
12
Maximum
Units
pF
k
Ω
k
Ω
pF
pF
Ω
ICS87004AG REVISION C DECEMBER 1, 2009
2
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. PLL Enable Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
Q[0:3]
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICS87004AG REVISION C DECEMBER 1, 2009
3
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q[0:3]
÷8
÷8
÷8
÷16
÷16
÷16
÷32
÷32
÷64
÷128
÷4
÷4
÷8
÷2
÷4
÷2
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ICS87004AG REVISION C DECEMBER 1, 2009
4
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
100
16
6
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
96
15
6
Units
V
V
V
mA
mA
mA
ICS87004AG REVISION C DECEMBER 1, 2009
5
©2009 Integrated Device Technology, Inc.
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