modes.Guaranteed bank, output, and par t-to-par t skew
character istics make the ICS87004-03 ideal for those
applications demanding well defined perfor mance and
repeatability.
• Output skew: 100ps (typical)
• Bank skew: 50ps (typical)
• Part-to-part skew: TBD
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
OEA
Pullup
NA2:NA0
Pulldown
3
CLK_SEL
Pulldown
CLK0
Pulldown
0
N Output Divider
NA2:NA0
0 0 0 ÷1 (default)
0 0 1 ÷2
0 1 0 ÷3
0 1 1 ÷4
1 0 0 ÷5
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
N Output Divider
NB2:NB0
0 0 0 ÷1 (default)
0 0 1 ÷2
0 1 0 ÷3
0 1 1 ÷4
1 0 0 ÷5
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
P
IN
A
SSIGNMENT
QA0
V
DD
NA2
NA1
NA0
CLK0
CLK_SEL
CLK1
NB2
NB1
NB0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OEA
V
DDOA
QA0
QA1
GND
QB1
QB0
V
DDOB
GND
OEB
QA1
V
DD0A
CLK1
Pulldown
1
V
DD0B
ICS87004-03
QB0
QB1
20-Lead TSSOP
6.50mm x 4.40mm x 0.92mm package body
G Package
Top View
NB2:NB0
Pulldown
OEB
Pullup
3
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
1
ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2 , 3, 4
5, 7
6
8, 9, 10
11
12, 16
13
14, 15
17, 18
19
Name
V
DD
NA2, NA1, NA0
CLK0, CLK1
CLK_SEL
NB2, NB1, NB0
OEB
GND
V
DDOB
QB0, QB1
QA1, QA0
V
DDOA
Power
Input
Input
Input
Input
Input
Power
Power
Output
Output
Power
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Type
Description
Power supply pin.
N divider pins for Bank A outputs.
LVCMOS / LVTTL interface levels.
LVCMOS / LVTTL clock inputs.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
N divider pins for Bank B outputs.
LVCMOS / LVTTL interface levels.
Output enable. When LOW, Bank B outputs are in HIGH
impedance state. When HIGH, Bank B outputs are active.
LVCMOS / LVTTL interface levels.
Power supply ground.
Output supply pin for Bank B outputs.
Bank B clock outputs. LVCMOS / LVTTL interface levels.
Bank A clock outputs. LVCMOS / LVTTL interface levels.
Bank A output supply pin.
Output enable. When LOW, Bank A outputs are in HIGH
impedance state. When HIGH, Bank A outputs are active.
20
OE A
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
TBD
15
Maximum
Units
pF
kΩ
kΩ
pF
Ω
T
ABLE
3. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
N2
0
0
0
0
1
1
1
Inputs
N1
0
0
1
1
0
0
1
N0
0
1
0
1
0
1
0
N Divider Value
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
Output Frequency (MHz)
Minimum
Maximum
1
1
1
÷16
NOTE: Some combinations of Bank A and Bank B output divider selections
are not synchronous.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
2
ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
93.1°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDOA
= V
DDOB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
40
1
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDOA
= V
DDOB
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
40
1
Maximum
3.465
2.625
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDOA
= V
DDOB
= 1.8V±0.15V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.65
Typical
3.3
1.8
40
1
Maximum
3.465
1.95
Units
V
V
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDOA
= V
DDOB
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
39
1
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDOA
= V
DDOB
= 1.8V±0.15V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.65
Typical
2.5
1.8
39
1
Maximum
2.625
1.95
Units
V
V
mA
mA
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
3
ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%V
DDOA
= V
DDOB
= 3.3V±5%, 2.5V±5%
OR
1.8V±0.15V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
Input High Voltage
Input Low Voltage
CLK0, CLK1, CLK_SEL,
NA2:NA0, NB2:NB0
OEA, OEB
CLK0, CLK1, CLK_SEL,
NA2:NA0, NB2:NB0
OEA, OEB
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDOX
= 3.3V ± 5%
V
DDOX
= 2.5V ± 5%
V
DDOX
= 1.8V ± 0.15V
V
DDOX
= 3.3V ± 5%
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
I
IH
Input
High Current
I
IL
Input
Low Current
-5
-150
2.6
1.8
1.5
0. 5
0. 5
0.4
-5
5
V
OH
Output High Voltage; NOTE 1
V
V
V
µA
µA
V
OL
I
OZL
I
OZH
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
V
DDOX
= 2.5V ± 5%
V
DDOX
= 1.8V ± 0.15V
NOTE 1: Outputs terminated with 50
Ω
to V
DDOX
/2. See Parameter Measurement Information, Output Load Test Circuit.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDOA
= V
DDOB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
sk(b)
t
R
/ t
F
odc
t
EN
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Par t-to-Par t Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time; NOTE 6
20% to 80%
4.5
100
TBD
50
800
50
5
5
Test Conditions
Minimum
Typical
Maximum
200
Units
MH z
ns
ps
ps
ps
ps
%
ns
ns
Output Disable Time; NOTE 6
t
DIS
All parameters measured at ƒ
≤
TBDMHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
4
ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDOA
= V
DDOB
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
sk(b)
t
R
/ t
F
odc
t
EN
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Par t-to-Par t Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time; NOTE 6
20% to 80%
4.5
100
TBD
50
850
50
5
5
Test Conditions
Minimum
Typical
Maximum
200
Units
MH z
ns
ps
ps
ps
ps
%
ns
ns
Output Disable Time; NOTE 6
t
DIS
All parameters measured at ƒ
≤
TBDMHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDOA
= V
DDOB
= 1.8V±0.15V, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
sk(b)
t
R
/ t
F
odc
t
EN
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Par t-to-Par t Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time; NOTE 6
20% to 80%
4.5
100
TBD
50
900
50
5
5
Test Conditions
Minimum
Typical
Maximum
200
Units
MH z
ns
ps
ps
ps
ps
%
ns
ns
Output Disable Time; NOTE 6
t
DIS
All parameters measured at ƒ
≤
TBDMHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
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