EEWORLDEEWORLDEEWORLD

Part Number

Search

XCV2000E-8FGG680I

Description
Field Programmable Gate Array, 9600 CLBs, 518400 Gates, 416MHz, 43200-Cell, CMOS, PBGA680, FBGA-680
CategoryProgrammable logic devices    Programmable logic   
File Size581KB,54 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance
Download Datasheet Parametric View All

XCV2000E-8FGG680I Overview

Field Programmable Gate Array, 9600 CLBs, 518400 Gates, 416MHz, 43200-Cell, CMOS, PBGA680, FBGA-680

XCV2000E-8FGG680I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeBGA
package instructionBGA, BGA680,39X39,40
Contacts680
Reach Compliance Codecompli
maximum clock frequency416 MHz
Combined latency of CLB-Max0.4 ns
JESD-30 codeS-PBGA-B680
JESD-609 codee1
length40 mm
Humidity sensitivity level3
Configurable number of logic blocks9600
Equivalent number of gates518400
Number of entries512
Number of logical units43200
Output times512
Number of terminals680
organize9600 CLBS, 518400 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA680,39X39,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)260
power supply1.2/3.6,1.8 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.9 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width40 mm
Base Number Matches1
0
R
Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array, shown in
Figure 1,
comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks (IOBs).
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex-E IOB,
Figure 2,
features SelectI/O+ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see
Table 1.
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
T
TCE
D Q
CE
Weak
Keeper
SR
DLLDLL
DLLDLL
O
OCE
D Q
CE
PAD
OBUFT
VersaRing
SR
I
IQ
Q
Programmable
Delay
IBUF
D
CE
BRAMs
BRAMs
BRAMs
BRAMs
CLBs
CLBs
CLBs
CLBs
IOBs
Vref
SR
SR
CLK
ICE
ds022_02_091300
IOBs
Figure 2:
Virtex-E Input/Output Block (IOB)
VersaRing
DLLDLL
DLLDLL
ds022_01_121099
Figure 1:
Virtex-E Architecture Overview
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM.
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
© 2000–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
www.xilinx.com
Module 2 of 4
1
Found a good document "Conventional test items for switching power supplies"
Through this introduction, we can know what requirements a switching power supply needs to meet and how to test it...
蓝雨夜 DIY/Open Source Hardware
Structural Programming
In the process of data packaging, how to load some of the recorded flags into the structure? Urgent help...
李嘉辉 Programming Basics
Help! How to view the pin definition in the Keil file for the STM32F103C8T6 chip?
Now I have a bunch of Keil files and a minimum system board for STM32C8T6, a UsartGPU serial port screen and a sensor, but I don’t know how to connect them together at the hardware level to achieve co...
小白16 stm32/stm8
F28335's SCI serial port cannot be adjusted
I need to build a board for my undergraduate graduation project, but the SCI serial port is not working. The data cannot be sent out... Please help me check if there are any errors in the schematic di...
jiangning456 Microcontroller MCU
Popular Science丨Six Elements of Brushless DC Motor Control
Rising consumer demands for power, reliability, functionality, and performance are driving the rapid development of electronic devices, including lawn mowers, refrigerators, vacuum cleaners, cars, and...
兰博 RF/Wirelessly
Play with HDMI2.1 source test
In the HDMI2.1 source test, the oscilloscope simulates the behavior of the sink and provides the termination resistance and termination voltage. The EDID simulator simulates the EDID of the sink and p...
火辣西米秀 Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1650  2195  2927  1905  2640  34  45  59  39  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号